HD64F2636F20J Renesas Electronics America, HD64F2636F20J Datasheet - Page 192

• Manufacturer Part Number: HD64F2636F20J
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an
instruction fetch, data read, data write, or data read/write cycle as the channel A break condition.
Bit 2
CSELA1
0
1
Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.
Bit 0
BIEA
0
1
6.2.4
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.2.5
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus
cycle, and module stop mode is entered. Register read/write accesses are not possible in module
stop mode. For details, see section 23A.5, 23B.5, Module Stop Mode.
MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.
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Bit
Initial value
Read/Write
Break Control Register B (BCRB)
Module Stop Control Register C (MSTPCRC)
Bit 1
CSELA0
0
1
0
1
Description
PC break interrupts are disabled
PC break interrupts are enabled
MSTPC7
R/W
7
1
Instruction fetch is used as break condition
Data read cycle is used as break condition
Data write cycle is used as break condition
Data read/write cycle is used as break condition
Description
MSTPC6
R/W
6
1
MSTPC5
R/W
5
1
MSTPC4
R/W
4
1
MSTPC3
R/W
3
1
MSTPC2
R/W
2
1
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
MSTPC1
R/W
1
1
(Initial value)
(Initial value)
MSTPC0
May 28, 2010
R/W
0
1