HD64F2636F20J Renesas Electronics America, HD64F2636F20J Datasheet - Page 195
![IC H8S MCU FLASH 128K 128QFP](/photos/28/61/286109/128-bfqfp_sml.jpg)
HD64F2636F20J
Manufacturer Part Number
HD64F2636F20J
Description
IC H8S MCU FLASH 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2636F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Price
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HD64F2636F20J
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HIT
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Part Number:
HD64F2636F20J
Manufacturer:
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H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
6.3.4
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
(1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
(2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
(3) When the SLEEP instruction causes a transition from subactive mode * to high-speed
(4) When the SLEEP instruction causes a transition to software standby mode or watch mode * :
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
REJ09B0103-0800 Rev. 8.00
May 28, 2010
sleep mode, or from subactive mode * to subsleep mode * :
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode * , and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2
(A)).
subactive mode * :
After execution of the SLEEP instruction, a transition is made to subactive mode * via direct
transition exception handling. After the transition, PC break interrupt handling is executed,
then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)).
(medium-speed) mode:
After execution of the SLEEP instruction, and following the clock oscillation settling time, a
transition is made to high-speed (medium-speed) mode via direct transition exception
handling. After the transition, PC break interrupt handling is executed, then the instruction at
the address after the SLEEP instruction is executed (figure 6-2 (C)).
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6-2
(D)).
U-mask and W-mask versions only.
Operation in Transitions to Power-Down Modes
Section 6 PC Break Controller (PBC)
Page 145 of 1458
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