M30291FATHP Renesas Electronics America, M30291FATHP Datasheet - Page 268

• Manufacturer Part Number: M30291FATHP
• Description: IC M16C MCU FLASH 96K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30291FATHP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 5
5.1.3 Hardware Interrupts
(1) Special interrupts
(2) Peripheral I/O interrupts
There are Two types in hardware Interrupts; special interrupts and Peripherai I/O interrupts.
Special interrupts are nonmaskable interrupts.
• Reset
• NMI interrupt
• DBC interrupt
• Watchdog timer interrupt
• Single-step interrupt
• Address-match interrupt
These interrupts are generated by the peripheral functions built into the microcomputer system. The
types of built-in peripheral functions vary with each M16C model, so do the types of interrupt causes. The
interrupt vector table uses the same software interrupt numbers 0–31 that are used by the INT instruction.
Peripheral I/O interrupts are maskable interrupts. For details about peripheral I/O interrupts, refer to the
M16C User’s Manual.
________
A reset occurs when the RESET pin is pulled low.
______
This interrupt occurs when the NMI pin is pulled low.
This interrupt is used exclusively for debugger purposes. You normally do not need to use this interrupt.
This interrupt is caused by the watchdog timer.
This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter-
rupt. A single-step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated
each time an instruction is executed.
This interrupt occurs when the program's execution address matches the content of the address match
register while the address match interrupt enable bit is set (= 1).
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.
Interrupt
____________
______
250
5.1 Outline of Interrupt