M30291FATHP Renesas Electronics America, M30291FATHP Datasheet - Page 273

• Manufacturer Part Number: M30291FATHP
• Description: IC M16C MCU FLASH 96K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30291FATHP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 5
Figure 5.3.1. Interrupt response time
Table 5.3.1 Interrupt Sequence Execution Time
*1 Add two cycles for the DBC interrupt. Add one cycle for the address match and single-step interrupts.
*2 Allocate interrupt vector addresses in even addresses as must as possible.
Interrupt vector address
5.3.1 Interrupt Response Time
(a) Time from when interrupt request is generated to when the instruction then under execution is completed
(b) Time in which the interrupt sequence is executed
The interrupt response time means a period of time from when an interrupt request is generated till when
the first instruction of the interrupt routine is executed. This period consists of time (a) from when an
interrupt request is generated to when the instruction then under way is completed and time (b) in which
an interrupt sequence is executed. Figure 5.3.1 shows the interrupt response time.
Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time
that consists of 30 cycles (without wait state) .
Time (b) is shown below.
Interrupt request generated
Odd address
Odd address
Even address
Even address
Interrupt
*2
*2
________
Instruction
Stack pointer (SP) value
Interrupt response time
(a)
Even address
Even address
Odd address
Odd address
Interrupt request acknowledged
Interrupt sequence
(b)
255
Without wait state
16 bits data bus
18 cycle
19 cycle
19 cycle
20 cycle
Instruction in interrupt
routine
*1
*1
*1
*1
Without wait state
5.3 Interrupt Sequence
8 bits data bus
Time
20 cycle
20 cycle
20 cycle
20 cycle
*1
*1
*1
*1