EE87C196MH Intel, EE87C196MH Datasheet - Page 12

• Manufacturer Part Number: EE87C196MH
• Description: IC MCU 16-BIT 5V 32K OTP 84-PLCC
• Manufacturer: Intel
• Series: 87Cr

Specifications of EE87C196MH

• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 744 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 863928

8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
PIN DESCRIPTIONS
12
ACH7
ACH6
ACH5
ACH4
ACH3:0
AD15:8
AD7:0
ADV#
AINC#
ALE
ANGND
BCLK1
BCLK0
Signal
Name
Type
GND
I/O
O
O
I
I
I
Analog Channels. These pins are analog inputs to the A/D
converter.
These pins are multiplexed with the port 0 pins. While it is
possible for the pins to function simultaneously as analog and
digital inputs, this is not recommended because reading the
port while a conversion is in process can produce unreliable
conversion results.
The ANGND and V
converter and the multiplexed port pins to function.
Address/Data Lines. These pins provide a multiplexed
address and data bus. During the address phase of the bus
cycle, address bits 0–15 are presented on the bus and can
be latched using ALE or ADV#. During the data phase, 8- or
16-bit data is transferred.
Address Valid. This active-low output signal is asserted only
during external memory accesses.
ADV# indicates that valid address information is available on
the system address/data bus. The signal remains low while a
valid bus cycle is in progress and is returned high as soon as
the bus cycle completes.
An external latch can use the ADV# signal to demultiplex the
address from the address/data bus. Used with a decoder,
ADV# can generate chip-selects for external memory.
Auto Increment. In slave programming mode, this active-low
input signal enables the autoincrement mode. Auto increment
allows reading from or writing to sequential OTPROM
locations without requiring address transactions across the
programming bus for each read or write.
Address Latch Enable. This active-high output signal is
asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates
that valid address information is available on the system
address/data bus. ALE differs from ADV# in that it is not
returned high until a new bus cycle is to begin.
An external latch can use ALE to demultiplex the address
from the address/data bus.
Analog Ground. Reference ground for the A/D converter
and the logic used to read port 0. ANGND must be held at
nominally the same potential as V
Serial Communications Baud Clock 0 and 1. BCLK0 and 1
are alternate clock sources for the serial ports. The maximum
input frequency is F
Table 7. Signal Descriptions
REF
OSC
pins must be connected for the A/D
/4.
Description
SS
.
P0.7/T1DIR/PMODE.3
P0.6/T1CLK/PMODE.2
P0.5/PMODE.1
P0.4/PMODE.0
P0.3:0
P4.7:0/PBUS.15:8
P3.7:0/PBUS.7:0
P5.0/ALE
P2.4/COMP0
P5.0/ADV#
—
P2.7/SCLK1#
P2.1/SCLK0#/PALE#
Multiplexed
With
®