EE87C196MH Intel, EE87C196MH Datasheet - Page 13

• Manufacturer Part Number: EE87C196MH
• Description: IC MCU 16-BIT 5V 32K OTP 84-PLCC
• Manufacturer: Intel
• Series: 87Cr

Specifications of EE87C196MH

• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 744 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 863928

BHE#
BUSWIDTH
COMP3
COMP2
COMP1
COMP0
CPVER
EA#
EPA1
EPA0
Signal
Name
®
Type
I/O
O
O
O
I
I
Byte High Enable. During 16-bit bus cycles, this active-low
output signal is asserted for word reads and writes and for
high-byte reads and writes to external memory. BHE#
indicates that valid data is being transferred over the upper
half of the system address/data bus.
BHE#, in conjunction with A0, selects the memory byte to be
accessed:
BHE#
Bus Width. When enabled in the chip configuration register,
this active-high input signal dynamically selects the bus width
of the bus cycle in progress. When BUSWIDTH is high, a 16-
bit bus cycle occurs; when BUSWIDTH is low, an 8-bit bus
cycle occurs. BUSWIDTH is active during a CCR fetch.
Event Processor Array (EPA) Compare Pins. These
signals are the output of the EPA compare modules. These
pins are multiplexed with other signals and may be
configured as standard I/O.
Cumulative Program Verification. This active-high output
signal indicates whether any verify errors have occurred
since the device entered programming mode. CPVER
remains high until a verify error occurs, at which time it is
driven low. Once an error occurs, CPVER remains low until
the device exits programming mode. When high, CPVER
indicates that all locations have programmed correctly since
the device entered programming mode.
External Access. This active-low input signal directs
memory accesses to on-chip or off-chip memory. If EA# is
low, the memory access is off-chip. If EA# is high and the
memory address is within 2000H–2FFFH, the access is to
on-chip ROM or OTPROM. Otherwise, an access with EA#
high is to off-chip memory.
EA# is sampled only on the rising edge of RESET#.
If EA# = V
the programming mode selected by PMODE.3:0.
For devices without ROM, EA# must be tied low.
Event Processor Array (EPA) Input/Output pins. These
are the high-speed input/output pins for the EPA
capture/compare modules. These pins are multiplexed with
other signals and may be configured as standard I/O.
0
0
1
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
A0
0
1
0
EA
Table 7. Signal Descriptions (Continued)
on the rising edge of RESET#, the device enters
Byte(s) Accessed
both bytes
high byte only
low byte only
Description
P5.5/WRH#
P5.7
P2.3
P2.6/CPVER
P2.5/PACT#
P2.4/AINC#
P2.6/COMP2
—
P2.2/PROG#
P2.0/PVER
Multiplexed
With
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