EE87C196MH Intel, EE87C196MH Datasheet - Page 14

• Manufacturer Part Number: EE87C196MH
• Description: IC MCU 16-BIT 5V 32K OTP 84-PLCC
• Manufacturer: Intel
• Series: 87Cr

Specifications of EE87C196MH

• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 744 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 863928

8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
14
EXTINT
INST
NMI
ONCE#
Signal
Name
Type
O
I
I
I
External Interrupt. This programmable interrupt is controlled
by the WG_PROTECT register. This register controls
whether the interrupt is edge triggered or sampled and
whether a rising edge/high level or falling edge/low level
activates the interrupt. This interrupt vectors through memory
location 203CH. If the chip is in idle mode and if EXTINT is
enabled, a valid EXTINT interrupt brings the chip back to
normal operation, where the first action is to execute the
EXTINT service routine. After completion of the service
routine, execution resumes at the instruction following the
one that put the chip into idle mode.
In powerdown mode, a valid EXTINT interrupt causes the
chip to return to normal operating mode. If EXTINT is
enabled, the EXTINT service routine is executed. Otherwise,
execution continues at the instruction following the IDLPD
instruction that put the chip into powerdown mode.
Instruction Fetch. This active-high output signal is valid only
during external memory bus cycles. When high, INST
indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle
of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configu-
ration byte reads. INST is low during internal memory
fetches.
Nonmaskable Interrupt. In normal operating mode, a rising
edge on NMI causes a vector through the NMI interrupt at
location 203EH. NMI must be asserted for greater than one
state time to guarantee that it is recognized.
In idle mode, a rising edge on NMI brings the chip back to
normal operation, where the first action is to execute the NMI
service routine. After completion of the service routine,
execution resumes at the instruction following the one that
put the chip into idle mode.
In powerdown mode, NMI causes a return to normal
operating mode only if it is tied to EXTINT.
On-circuit Emulation. Holding this pin low while the
RESET# signal transitions from a low to a high places the
device into on-circuit emulation (ONCE) mode. ONCE mode
isolates the device from other components in the system to
allow the use of a clip-on emulator for system debugging.
This mode puts all pins except XTAL1 and XTAL2 into a high-
impedance state. To exit ONCE mode, reset the device by
pulling the RESET# signal low.
Table 7. Signal Descriptions (Continued)
Description
—
P5.1
—
P5.4
Multiplexed
With
®