M30263F6AFP#U9 Renesas Electronics America, M30263F6AFP#U9 Datasheet
M30263F6AFP#U9
Specifications of M30263F6AFP#U9
Related parts for M30263F6AFP#U9
M30263F6AFP#U9 Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
M16C/26A Group 16 (M16C/26A, M16C/26B, M16C/26T) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is ...
Page 4
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
Page 5
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
Page 6
How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
Page 7
Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
Page 8
Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 XXX4 XXX5 XXX6 XXX7 *1 Blank: Set ...
Page 9
List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. IEBus is ...
Page 10
Table of Contents Quick Reference by Address _______________________ B-1 1. Overview ______________________________________ 1 1.1 Applications ................................................................................................................... 1 1.2 Performance Outline ..................................................................................................... 2 1.3 Block Diagram ............................................................................................................... 4 1.4 Product List ................................................................................................................... 6 1.5 Pin Assignments .......................................................................................................... 11 1.6 Pin Description ...
Page 11
Reset ________________________________________ 26 5.1 Hardware Reset .......................................................................................................... 26 5.1.1 Hardware Reset 1 ................................................................................................ 26 5.1.2 Hardware Reset 2 ................................................................................................ 26 5.2 Software Reset ............................................................................................................ 27 5.3 Watchdog Timer Reset ................................................................................................ 27 5.4 Oscillation Stop Detection Reset ................................................................................. 27 5.5 ...
Page 12
Interrupts and Interrupt Vector .................................................................................... 64 9.2.1 Fixed Vector Tables .............................................................................................. 64 9.2.2 Relocatable Vector Tables ................................................................................... 65 9.3 Interrupt Control .......................................................................................................... 66 9.3.1 I Flag .................................................................................................................... 69 9.3.2 IR Bit .................................................................................................................... 69 9.3.3 ILVL2 to ILVL0 Bits and ...
Page 13
Three-phase Motor Control Timer Function ............................................................ 117 12.3.1 Position-data-retain Function ........................................................................... 128 12.3.2 Three-phase/Port Output Switch Function ....................................................... 130 13. Serial I/O ___________________________________ 132 13.1. UARTi (i=0 to 2)...................................................................................................... 132 13.1.1. Clock Synchronous serial I/O Mode ................................................................ 142 13.1.2. ...
Page 14
Memory Map ........................................................................................................... 232 17.3 Functions To Prevent Flash Memory from Rewriting............................................... 235 17.3.1 ROM Code Protect Function ............................................................................ 235 17.3.2 ID Code Check Function .................................................................................. 235 17.4 CPU Rewrite Mode ................................................................................................. 237 17.4.1 EW0 Mode ....................................................................................................... 238 17.4.2 ...
Page 15
Electrical Characteristics _______________________ 261 18.1. M16C/26A, M16C/26B (Normal version) ................................................................ 261 18.2. M16C/26T (T version) ............................................................................................ 280 19. Usage Notes ________________________________ 299 19.1 SFR ......................................................................................................................... 299 19.1.1 Precaution for 48-pin package ......................................................................... 299 19.1.2 Precaution for 42-pin package ......................................................................... ...
Page 16
Flash Memory Version .......................................................................................... 320 19.13.1 Functions to Inhibit Rewriting Flash Memory ................................................. 320 19.13.2 Stop mode ...................................................................................................... 320 19.13.3 Wait mode ...................................................................................................... 320 19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode... 320 19.13.5 Writing command ...
Page 17
Quick Reference by Address Register Address 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 0004 16 Processor mode register 1 0005 16 System clock control register 0 0006 16 System clock control register 1 0007 16 ...
Page 18
Quick Reference by Address Register Address 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01B0 16 01B1 16 01B2 16 01B3 Flash memory control register 4 16 01B4 16 Flash memory control register 1 ...
Page 19
Quick Reference by Address Register Address Count start flag 0380 16 Clock prescaler reset flag 0381 16 One-shot start flag 0382 16 Trigger select register 0383 16 Up-down flag 0384 16 0385 16 0386 16 Timer A0 register 0387 16 ...
Page 20
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview The M16C/26A Group (M16C/26A, M16C/26B, M16C/26T single-chip control MCU, fabricated using high-performance silicon gate CMOS technology, embedding ...
Page 21
1.2 Performance Outline Table 1.1 and 1.2 outline performance overview of the M16C/26A Group (M16C/26A, M16C/26B, M16C/ ...
Page 22
Table 1.2. Performance outline of M16C/26A group (M16C/26A, M16C/26B) (42-pin package) Item CPU Basic instructions Minimun ...
Page 23
1.3 Block Diagram Figure 1.1 and 1.2 show block diagrams of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) ...
Page 24
Port P6 Port P1 Peripheral functions Timer (16-bit) Output (timer A): 5channels Input (timer B): ...
Page 25
1.4 Product List Tables 1.3 to 1.6 lists product information, Figure 1.3 shows a product numbering system, ...
Page 26
Type No XXX ...
Page 27
Table 1.7 Product Code (Flash Memory Version) - M16C/26A, M16C/26B ...
Page 28
(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26A, M16C/26B 0260F8A XXXXX (2) Flash memory version, PRSP0042GA-B (42P2R), ...
Page 29
(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T T-ver. 0260F8T XXXXX (2) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T ...
Page 30
1.5 Pin Assignments Figures 1.6 and 1.7 show the Pin Assignments (top view). P10 /AN /KI ...
Page 31
Table 1.11 Pin Characteristics for 48-Pin Package ...
Page 32
P10 / REF /TB1 ...
Page 33
Table 1.12 Pin Characteristics for 42-Pin Package ...
Page 34
1.6 Pin Description Table 1.13 Pin Description (48-Pin and 42-Pin Packages) Classification Pin Name I/O Type ...
Page 35
Table 1.13 Pin Description ( 48-pin packages only) (Continued) Classification Pin Name _________ Serial I/O CTS0 ...
Page 36
Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised ...
Page 37
2.3 Frame Base Register (FB configured with 16 bits, and is used for FB ...
Page 38
Memory Figure 3 memory map of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T). The ...
Page 39
Special Function Registers (SFRs) Table 4.1 SFR Information(1) Address 0000 16 0001 16 0002 16 ...
Page 40
Table 4.2 SFR Information(2) Address 0040 16 0041 16 0042 16 0043 16 INT3 interrupt control ...
Page 41
Table 4.3 SFR Information(3) Address 0080 16 0081 16 0082 16 0083 16 0084 16 0085 ...
Page 42
Table 4.4 SFR Information(4) Address 0340 16 0341 16 Timer A1-1 register 0342 16 0343 16 ...
Page 43
Table 4.5 SFR Information(5) Address Count start flag 0380 16 0381 Clock prescaler reset flag 16 ...
Page 44
Table 4.6 SFR Information(6) Address A/D register 0 03C0 16 03C1 16 A/D register 1 03C2 ...
Page 45
Reset There are four types of resets: a hardware reset, a software reset, an watchdog ...
Page 46
RESET CC Figure 5.1.1.1. Example Reset Circuit 5.2 Software Reset When the PM03 bit in ...
Page 47
ROC td(P-R) More than td(ROC) RESET CPU clock Address Figure 5.1.1.2. Reset Sequence Table ...
Page 48
5.5 Voltage Detection Circuit Note assumed. Voltage Detection Circuit is not available ...
Page 49
...
Page 50
Vdet4 Vdet3r VCC Vdet3 Vdet3s VSS RESET Internal Reset Signal VC13 bit in VCR1 register VC26 ...
Page 51
5.5.1 Voltage Down Detection Interrupt If the D40 bit in the D4INT register is set to ...
Page 52
Voltage Down Detection Circuit D4INT clock(the clock with which it VC27 operates also in wait mode) ...
Page 53
5.5.2 Limitations on Exiting Stop Mode The voltage down detection interrupt is immediately generated and the ...
Page 54
Processor Mode The microcomputer supports single-chip mode only. Figures 6.1 and 6.2 show the associated ...
Page 55
Processeor Mode Register NOTES: 1. Write ...
Page 56
The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) ...
Page 57
Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock ...
Page 58
CM10=1(stop mode WAIT instruction R RESET Software reset NMI Interrupt request level ...
Page 59
System clock control register NOTES: 1. Write to ...
Page 60
System clock control register 1 ( Symbol 0 0 ...
Page 61
Oscillation stop detection register ( NOTES: 1. ...
Page 62
Peripheral Clock Select Register NOTE: ...
Page 63
PLL control register NOTES: 1. Write ...
Page 64
The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock ...
Page 65
7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is ...
Page 66
7.3 On-chip Oscillator Clock This clock is supplied by a on-chip oscillator. This clock is used as ...
Page 67
Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00 (CM16 and ...
Page 68
7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and ...
Page 69
7.6 Power Control There are three power control modes. For convenience’ sake, all modes other than wait ...
Page 70
7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided ...
Page 71
7.6.2.3 Pin Status During Wait Mode Table 7.6.2.3.1 lists pin status during wait mode. Table 7.6.2.3.1 Pin ...
Page 72
7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock ...
Page 73
Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure ...
Page 74
Main clock oscillation PLL operation mode PLC07=1 CM11=1 CPU clock: f(PLL) (5) CM07=0 CM06=0 CM17=0 PLC07=0 CM16=0 ...
Page 75
Table 7.6.1. Allowed Transition and Setting High-speed mode, middle-speed mode High-speed mode, 8 middle-speed mode Low-speed mode ...
Page 76
7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this ...
Page 77
7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset) When main clock ...
Page 78
7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect ...
Page 79
Protection Note The PRC3 bit in the PRCR register is not available in M16C/26T. In the ...
Page 80
Interrupt Note The 42-pin package does not use UART0 transmission interrupt and UART0 reception interrupt ...
Page 81
9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. ...
Page 82
9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function ...
Page 83
9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address ...
Page 84
9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB ...
Page 85
9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set ...
Page 86
Interrupt control register NOTES: 1.This bit can only ...
Page 87
Interrupt request cause select register NOTE: 1. When setting ...
Page 88
9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag ...
Page 89
9.4 Interrupt Sequence An interrupt sequence (the devicebehavior from the instant an interrupt is accepted to ...
Page 90
9.4.1 Interrupt Response Time Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt ...
Page 91
9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the ...
Page 92
The operation of saving registers carried out in the interrupt sequence is dependent on whether the ...
Page 93
9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which ...
Page 94
Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 INT3 INT2 ...
Page 95
______ 9.6 INT Interrupt _______ INTi interrupt (i triggered by the edges of ...
Page 96
______ 9.7 NMI Interrupt _______ An NMI interrupt request is generated when input on the NMI ...
Page 97
9.9 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction ...
Page 98
Address match interrupt enable register Address match interrupt ...
Page 99
10. Watchdog Timer The watchdog timer is the function that detects when a program is out ...
Page 100
Watchdog Timer Control Register Watchdog Timer Start Register ...
Page 101
11. DMAC Note Do not use UART0 transfer and UART0 reception interrupt request as a DMA ...
Page 102
Table 11.1 DMAC Specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred (1, ...
Page 103
DMA0 request cause select register NOTE: 1. The ...
Page 104
DMA1 request cause select register NOTE: 1. The causes ...
Page 105
DMAi source pointer ( (b19) (b16)(b15) (b23 NOTE: 1. ...
Page 106
11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle ...
Page 107
(1) When the transfer unit bits and the source of transfer is ...
Page 108
11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. ...
Page 109
11.3 DMA Enable When a data transfer starts after setting the DMAE bit in DMiCON register ...
Page 110
11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer ...
Page 111
12. Timer Note The TB2IN pin is not available in the 42-pin package. Do not use ...
Page 112
1/2 • Main clock f 1 • PLL clock • On-chip 1/8 oscillator clock f f ...
Page 113
12.1 Timer A Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to ...
Page 114
Timer Ai register ( (1) (b15) (b8 NOTES: 1. The ...
Page 115
One-shot start flag NOTES: 1. Make sure the ...
Page 116
12.1.1. Timer Mode In timer mode, the timer counts a count source generated internally (see Table ...
Page 117
12.1.2. Event Counter Mode In event counter mode, the timer counts pulses from an external device ...
Page 118
Timer Ai mode register (i (When not using two-phase pulse signal processing ...
Page 119
Table 12.1.2.2. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 ...
Page 120
Timer Ai mode register (i (When using two-phase pulse signal processing ...
Page 121
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to ...
Page 122
12.1.3. One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one ...
Page 123
Timer Ai mode register (i ...
Page 124
12.1.4. Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given ...
Page 125
Timer Ai mode register ( ...
Page 126
Count source Input signal to TA pin iIN PWM pulse output from TA pin iOUT IR ...
Page 127
12.2 Timer B Note The TB2 pin for Timer B2 is not available in 42-pin package. IN ...
Page 128
Timer Bi mode register (i Bit symbol ...
Page 129
Timer Bi register (i=0 to 2)(1) (b15) (b8 NOTES: 1. The register must be ...
Page 130
12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). ...
Page 131
12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or ...
Page 132
12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the ...
Page 133
Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing at which counter reaches “0000 ...
Page 134
12.2.4 A/D Trigger Mode A/D trigger mode is used as conversion start trigger for A/D converter in ...
Page 135
Timer Bi mode register ( ...
Page 136
12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to ...
Page 137
Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram page 118 ...
Page 138
Three-phase PWM control register 0 ( NOTES: 1. ...
Page 139
Three-phase PWM control register NOTES: 1. ...
Page 140
Three-phase output buffer register(i=0, NOTE: 1. The IDB0 and ...
Page 141
Timer Ai, Ai-1 register (i= (b15) (b8 NOTES: 1. The register ...
Page 142
Timer B2 Special Mode Register Bit ...
Page 143
(1) Timer B2 register (b15) (b8 NOTE: 1. The register must be accessed ...
Page 144
Timer Ai mode register ...
Page 145
The three-phase motor control timer function is enabled by setting the INV02 bit in the VC0 ...
Page 146
Carrier wave: sawtooth waveform Carrier wave Signal wave Timer B2 Start trigger signal for timer A4* ...
Page 147
12.3.1 Position-data-retain Function This function is used to retain the position data synchronously with the three-phase ...
Page 148
12.3.1.2 Position-data-retain Function Control Register Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register. ...
Page 149
12.3.2 Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to “1”(Timer ...
Page 150
Port function control register NOTE: 1. This register is ...
Page 151
13. Serial I/O Note UART0 is not available in the 42-pin package. Serial I/O is configured ...
Page 152
(UART0) RxD 0 Clock source selection CLK1 to CLK0 1SIO or 2SIO Internal ...
Page 153
PAR 1SP disabled STPS PAR RxDi STPS=1 2SP enabled 0 0 PAR STPS=1 enabled ...
Page 154
reverse RxD data RxD2 reverse circuit Reverse 1SP STPS STPS=1 2SP 0 0 STPS=1 ...
Page 155
UARTi Transmit Buffer Register (i (b15) (b8 NOTES: 1. Use MOV ...
Page 156
UARTi transmit/receive mode register ( Bit ...
Page 157
UARTi Transmit/receive Control Rregister 0 (i ...
Page 158
UARTi Transmit/receive Control Register 1 (i= Symbol TE ...
Page 159
UART2 Special Mode Register Symbol IICM ABC ...
Page 160
UART2 special mode register NOTES: 1. The DL2 ...
Page 161
13.1.1. Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock ...
Page 162
Table 13.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit ...
Page 163
Table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table ...
Page 164
(1) Example of Transmit Timing (Internal clock is selected) Transfer clock “1” UiC1 register “0” Write data ...
Page 165
13.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving ...
Page 166
13.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register ( ...
Page 167
13.1.1.5 Serial data logic switch function (UART2) When the U2LCH bit in the U2C1 register is ...
Page 168
_______ _______ 13.1.1.7 CTS/RTS separate function (UART0) This function separates CTS from the P6 pin. To use ...
Page 169
13.1.2. Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after ...
Page 170
Table 13.1.2.2. Registers to Be Used and Settings in UART Mode Register Bit UiTB ...
Page 171
Table 13.1.2.3 lists the functions of the input/output pins during UART mode. Table 13.1.2.4 lists the ...
Page 172
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ...
Page 173
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop ...
Page 174
13.1.2.2. Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART ...
Page 175
13.1.2.4. Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its ...
Page 176
_______ _______ 13.1.2.6. CTS/RTS Separate Function (UART0) This function separates CTS from the P6 pin. To use ...
Page 177
13.1.3 Special Mode bus mode is provided for use as a ...
Page 178
SDA2 Delay circuit ACKC=1 ACKD bit Noise Filter Falling edge detection SCL2 IICM=0 STSPSEL=0 UART2 IICM=1 ...
Page 179
Table 13.1.3.2. Registers to Be Used and Settings in I Register Bit U2TB ...
Page 180
Table 13.1.3.3. Registers to Be Used and Settings in I Register Bit U2SMR4 STAREQ RSTAREQ STPREQ ...
Page 181
Table 13.1.3. bus Mode Functions Clock synchronous serial I/O Function mode (SMD2 to ...
Page 182
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH ...
Page 183
13.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been ...
Page 184
Table 13.1.3.2.1. STSPSEL Bit Functions Function Output of SCL2 and SDA2 pins Start/stop condition interrupt request ...
Page 185
13.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure ...
Page 186
13.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to “0” ...
Page 187
13.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock ...
Page 188
Microcomputer (Master) Figure 13.1.4.1. Serial Bus Communication Control Example (UART2) page 169 ...
Page 189
Table 13.1.4.2. Registers to Be Used and Settings in Special Mode 2 Register Bit (1) U2TB ...
Page 190
13.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can ...
Page 191
"H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) ...
Page 192
13.1.5 Special Mode 3 (IE Bus mode )(UART2) In this mode, one bit of IE Bus ...
Page 193
(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select) If ABSCS=0, ...
Page 194
13.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface ...
Page 195
Table 13.1.6.2. Registers to Be Used and Settings in SIM Mode Register Bit (1) U2TB 0 ...
Page 196
(1) Transmit Timing Transfer Clock "1" TE bit in U2C1 register "0" TI bit in U2C1 ...
Page 197
Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect T pull-up. Figure 13.1.6.2. SIM ...
Page 198
13.1.6.2 Format • Direct Format Set the PRY bit in the U2MR register to “1”, the ...
Page 199
14. A/D Converter Note P9 and P9 ( not ...
Page 200
CKS2=0 f 1/3 AD CKS2=1 V REF Resistor ladder VCUT VCUT=1 Successive conversion register ...