M30263F6AFP#U9 Renesas Electronics America, M30263F6AFP#U9 Datasheet - Page 100
M30263F6AFP#U9
Manufacturer Part Number
M30263F6AFP#U9
Description
MCU 3/5V 48K PB-FREE 42-SSOPP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U9
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
10.1 Count Source Protective Mode
. v
1
J
Figure 10.2 WDC Register and WDTS Register
0
6
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer
can be kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count
source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit to “1” results in the following conditions
2
9
C
• The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main
• The on-chip oscillator starts oscillating, and the in-chip oscillator clock becomes the watchdog timer count
• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
• The watchdog timer does not stop when in wait mode.
0 .
B
clock or PLL clock) (system clock of count source selected by the CM21 bit is valid)
source.
entered.)
2 /
0
0
Watchdog Timer Start Register
b7
6
2
0
A
Watchdog Timer Control Register
F
b7
2
e
0 -
G
b
b6
0
1 .
2
o r
0
, 5
u
0
b5
0
p
2
0
(
Watchdog timer period =
b4
0
M
7
1
b3
6
C
page 81
2 /
b2
6
, A
b1
b0
M
b0
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF
regardless of whatever value is written.
f o
1
6
3
C
Bit Symbol
Symbol
WDTS
2
(b6-b5)
(b4-b0)
2 /
WDC7
9
6
Symbol
WDC
, B
M
1
6
Watchdog timer count (32768)
C
Reserved bit
Prescaler select bit
High-order bit of watchdog timer
on-chip oscillator clock
2 /
6
) T
Bit Name
Address
000F
Address
000E
16
16
Function
After Reset
Indeterminate
Set to “0”
0: Divided by 16
1: Divided by 128
After Reset
00XXXXXX
Function
2
16
”
10. Watchdog Timer
RW
RW
RO
RW
RW
WO
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