MC908QY1AMDWER Freescale Semiconductor, MC908QY1AMDWER Datasheet - Page 39

• Manufacturer Part Number: MC908QY1AMDWER
• Description: IC MCU 8BIT 1.5K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY1AMDWER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The
output of the input multiplexer (ADVIN) is converted by a successive approximation algorithm into a 10-bit
digital result. When the conversion is completed, the result is placed in the data registers (ADRH and
ADRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADRL. The conversion complete flag
is then set and an interrupt is generated if the interrupt has been enabled.
3.3.1 Clock Select and Divide Circuit
The clock select and divide circuit selects one of three clock sources and divides it by a configurable value
to generate the input clock to the converter (ADCK). The clock can be selected from one of the following
sources:
Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If
the available clocks are too slow, the ADC10 will not perform according to specifications. If the available
Freescale Semiconductor
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MCU STOP
The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock
source which is enabled when the ADC10 is converting and the clock source is selected by setting
the ACLKEN bit. When the ADLPC bit is clear, this clock operates from 1–2 MHz; when ADLPC is
set it operates at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop
mode for lower noise operation.
Alternate Clock Source — This clock source is equal to the external oscillator clock or a four times
the bus clock. The alternate clock source is MCU specific, see
and availability of this clock source option. This clock is selected when ADICLK and ACLKEN are
both low.
The bus clock — This clock source is equal to the bus frequency. This clock is selected when
ADICLK is high and ACLKEN is low.
ADHWT
V
V
REFH
REFL
AD0
ADn
1
ADVIN
ADSCR
2
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
CONTROL SEQUENCER
Figure 3-2. ADC10 Block Diagram
DATA REGISTERS ADRH:ADRL
SAR CONVERTER
ADCK
ADCLK
CLOCK
DIVIDE
COCO
AIEN
1
2
3.1 Introduction
ACLK
ACLKEN
BUS CLOCK
ALTERNATE CLOCK SOURCE
GENERATOR
ASYNC
CLOCK
Functional Description
to determine source
INTERRUPT
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