MC908QY1AMDWER Freescale Semiconductor, MC908QY1AMDWER Datasheet - Page 41

• Manufacturer Part Number: MC908QY1AMDWER
• Description: IC MCU 8BIT 1.5K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY1AMDWER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive
state. In this state, all internal clocks and references are disabled. This state is entered asynchronously
and immediately upon aborting of a conversion.
3.3.3.4 Total Conversion Time
The total conversion time depends on many factors such as sample time, bus frequency, whether
ACLKEN is set, and synchronization time. The total conversion time is summarized in
The maximum total conversion time for a single conversion or the first conversion in continuous
conversion mode is determined by the clock source chosen and the divide ratio selected. The clock
source is selectable by the ADICLK and ACLKEN bits, and the divide ratio is specified by the ADIV bits.
For example, if the alternate clock source is 16 MHz and is selected as the input clock source, the input
clock divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single
10-bit conversion is:
Freescale Semiconductor
8-Bit Mode (short sample — ADLSMP = 0):
8-Bit Mode (long sample — ADLSMP = 1):
10-Bit Mode (short sample — ADLSMP = 0):
10-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f
Maximum Conversion time =
The ADCK frequency must be between f
maximum to meet A/D specifications.
Table 3-1. Total Conversion Time versus Control Conditions
Conversion Mode
Number of bus cycles = 11.25 μs x 4 MHz = 45 cycles
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
Bus
Bus
Bus
Bus
≥ f
≥ f
≥ f
≥ f
ADCK
ADCK
ADCK
ADCK
)
)
)
)
21 ADCK cycles
16 MHz/8
NOTE
ACLKEN
ADCK
X
X
X
X
0
1
0
1
0
1
0
1
+
minimum and f
3 bus cycles
4 MHz
38 ADCK + 3 bus clock + 5 μs
21 ADCK + 3 bus clock + 5 μs
41 ADCK + 3 bus clock + 5 μs
18 ADCK + 3 bus clock + 5 μs
Maximum Conversion Time
18 ADCK + 3 bus clock
38 ADCK + 3 bus clock
21 ADCK + 3 bus clock
41 ADCK + 3 bus clock
ADCK
16 ADCK
36 ADCK
19 ADCK
39 ADCK
= 11.25 μs
Functional Description
Table
3-1.
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