MC9S08RD32CPE Freescale Semiconductor, MC9S08RD32CPE Datasheet - Page 199

• Manufacturer Part Number: MC9S08RD32CPE
• Description: IC MCU 32K FLASH 2K RAM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CPE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

1
15.4.3
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
15.4.3.1
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
15.4.3.2
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
15.4.3.3
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
15.4.3.4
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
Freescale Semiconductor
Reset
BDFR is writable only through serial active background mode debug commands, not from user programs.
BDFR
Field
W
0
R
DBG Registers and Control Bits
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
0
0
7
Debug Comparator A High Register (DBGCAH)
Debug Comparator A Low Register (DBGCAL)
Debug Comparator B High Register (DBGCBH)
Debug Comparator B Low Register (DBGCBL)
Figure 15-6. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
0
0
6
Table 15-3. SBDFR Register Field Description
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
0
0
5
0
1
4
Description
0
0
3
0
0
2
1
0
0
Development Support
BDFR
0
0
0
1
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