MC9S12E256VFUE Freescale Semiconductor, MC9S12E256VFUE Datasheet - Page 64

• Manufacturer Part Number: MC9S12E256VFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 8 bit, 2 Channel
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 50 MHz
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1)
programmable to either falling edge-sensitive triggering or level-sensitive triggering based on the setting
of the IRQE bit in the IRQCR register. The IRQ is always enabled and configured to level-sensitive
triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active
pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing
PUPEE in the PUCR register.
1.4.15
PE0 is always an input and can always be read. The PE0 pin is also the XIRQ input for requesting a
nonmaskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register
(CCR) is set and any XIRQ interrupt is masked until MCU software enables it by clearing the X bit.
Because the XIRQ input is level sensitive triggered, it can be connected to a multiple-source wired-OR
network. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can
be turned off by clearing PUPEE in the PUCR register.
1.4.16
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, this pin is used as the emulation chip select output (ECS). In expanded
modes the PK7 pin can be used to determine the reset state of the ROMON bit in the MISC register. At
the rising edge of RESET, the state of the PK7 pin is latched to the ROMON bit. There is an active pull-up
on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPKE
in the PUCR register. Refer to
details. PK7 is not available in the 80 pin package version.
1.4.17
PK6 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, this pin is used as an external chip select signal for most external
accesses that are not selected by ECS. There is an active pull-up on this pin while in reset and immediately
out of reset. The pullup can be turned off by clearing PUPKE in the PUCR register. Refer to
“Multiplexed External Bus Interface (MEBIV3)”
package version.
1.4.18
PK[5:0] are general purpose input or output pins. In MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, PK[5:0] provide the expanded address XADDR[19:14] for the external
bus. There are active pull-ups on PK[5:0] pins while in reset and immediately out of reset. The pullup can
be turned off by clearing PUPKE in the PUCR register. Refer to
Interface (MEBIV3)”
64
PE0 / XIRQ — Port E input Pin 0 / Non Maskable Interrupt Pin
PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK6 / XCS — Port K I/O Pin 6
PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
for further details. PK[5:0] are not available in the 80 pin package version.
Chapter 18, “Multiplexed External Bus Interface (MEBIV3)”
MC9S12E256 Data Sheet, Rev. 1.08
for further details. PK6 is not available in the 80 pin
Chapter 18, “Multiplexed External Bus
Freescale Semiconductor
Chapter 18,
for further