HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 857
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 857 of 1418
- Download datasheet (9Mb)
Bit
14 to 2
1
0
• Write
Initial value:
Initial value:
Bit
31
30 to 18
17
R/W:
R/W:
Bit:
Bit:
CRWE
DRWE
Bit Name
⎯
OCI
LPS
Bit Name
CRWE
⎯
OCIC
31
15
W
W
0
0
30
14
-
R
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
0
0
Initial Value
0
All 0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
26
10
R
R
0
0
R
-
-
W
R/W
R
R
R/W
W
R
25
R
R
-
-
0
9
0
Description
Reserved
These bits are always read as 0.
Overcurrent Indicator
This bit reports overcurrent conditions when the
global reporting is implemented. When set, an
overcurrent condition exists. When cleared, all
power operations are normal. If per-port overcurrent
protection is implemented, this bit is always 0.
0: No port is in overcurrent state
1: A port is in overcurrent state
Local Power Status
The root hub does not support the local power
status function, thus, this bit is always read as 0.
Description
Clear Remote Wakeup Enable
Writing 1 to this bit clears the DRWE bit to 0. Writing
0 has no effect.
0: Operation is not affected
1: The DRWE bit is cleared to 0
Reserved
Always write 0 to this bit.
Overcurrent Indicator Change
HCD clears this bit to 0 by writing 1. Writing 0 has
no effect.
0: Operation is not affected
1: The OCIC bit is cleared to 0
24
R
R
0
8
0
-
-
23
R
R
0
0
7
-
-
Rev. 2.00 Feb. 12, 2010 Page 773 of 1330
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
19
R
R
0
3
0
-
-
REJ09B0554-0200
18
R
R
0
2
0
-
-
OCIC
OCI
17
W
R
0
1
0
LPSC
LPS
16
W
W
0
0
0
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