M30263F6AFP#U9A Renesas Electronics America, M30263F6AFP#U9A Datasheet - Page 257

• Manufacturer Part Number: M30263F6AFP#U9A
• Description: IC M16C/26A MCU FLASH 42-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30263F6AFP#U9A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 33
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
1
. v
J
6
0
C
17.4.1 EW0 Mode
17.4.2 EW1 Mode
2
9
0 .
2 /
B
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by
setting the FMR11 bit in the FMR1 register to “0”.
When setting the FMR01 bit to “1”, set to “1” after first writing “0”. The software commands control pro-
gramming and erasing. The FMR0 register or the status register indicates whether a programming or
erasing operations is completed.
When entering the erase-suspend during the auto-erasing, set the FMR40 bit to “1” (erase-suspend
enabled) and the FMR41 bit to “1” (suspend request). And wait for td(SR-ES). After verifying the FMR46
bit is set to “1” (auto-erase stop), access to the user ROM area. When setting the FMR41 bit to “0” (erase
restart), auto-erasing is restarted.
EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (set to “1” after first
writing “0”). The FMR0 register indicates whether or not a programming or an erasing operation is com-
pleted. Do not execute the software commands of read status register in EW1 mode.
When an erase/program operation is initiated the CPU halts all program execution until the operation is
completed or erase-suspend is requested.
When enabling an erase suspend function, set the FMR40 bit to “1” (erase suspend enabled) and ex-
ecute block erase commands. Also, preliminarily set an interrupt to enter the erase-suspend to an inter-
rupt enabled status. After td(SR-ES) from an interrupt request and entering erase suspend, an interrupt
can be acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically set to “1” (suspend request) and
an auto-erasing is halted. If an auto-erasing is not completed (the FMR00 bit is “0”) after an interrupt
process completed, set the FMR41 bit to “0” (erase restart) and execute block erase commands again.
0
0
6
2
A
0
F
2
e
G
0 -
b
o r
1 .
2
0
u
, 5
0
p
2
(
0
M
0
1
7
6
C
page 238
2 /
6
, A
M
1
f o
6
C
3
2
2 /
9
6
, B
M
1
6
C
2 /
6
) T
17. Flash Memory Version