MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 136

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
Technical Data
IRVNE — Internal read visibility/not E (refer to
On-Chip
LSBF — LSB first enable
SPR2 — SPI clock rate select
Bits 1, 0 — not implemented; always read zero.
Freescale Semiconductor, Inc.
In single chip mode this bit determines whether the E clock drives
out from the chip.
If this bit is set, data, which is usually transferred MSB first, is
transferred LSB first. LSBF does not affect the position of the MSB
and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain.
With the two bits in the SPCR, this bit specifies the SPI clock rate.
Refer to
For More Information On This Product,
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
Memory)
Serial Peripheral Interface (SPI)
Table
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7-1.
Operating Modes and
MC68HC11P2 — Rev 1.0