MC9S08DV48MLF Freescale Semiconductor, MC9S08DV48MLF Datasheet - Page 237
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MC9S08DV48MLF
Manufacturer Part Number
MC9S08DV48MLF
Description
IC MCU 48K FLASH 2K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV48MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV48MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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12.3.14 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
12.3.15 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Reset:
Reset
Figure 12-19. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
W
W
R
R
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
AC7
0
7
0
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Filter”).
Figure 12-18. MSCAN Transmit Error Counter (CANTXERR)
TXERR6
= Unimplemented
AC6
0
6
6
0
MC9S08DV60 Series Data Sheet, Rev 3
TXERR5
AC5
0
5
0
5
TXERR4
NOTE
AC4
0
4
4
0
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
TXERR3
AC3
0
0
3
3
TXERR2
AC2
2
0
2
0
TXERR1
AC1
Section 12.4.1,
0
Section 12.5.3,
1
0
1
TXERR0
AC0
0
0
0
0
237
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