DS87C550-QNL Maxim Integrated Products, DS87C550-QNL Datasheet - Page 35

• Manufacturer Part Number: DS87C550-QNL
• Description: IC MCU EPROM ADC/PWM HS 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 87Cr

Specifications of DS87C550-QNL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-LCC, 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

NOTES FOR DS87C550 DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
These parameters are guaranteed by design.
1. Voltage referenced to digital ground (GND).
2. Active current measured with 33MHz clock source on XTAL1, V
3. Idle mode current measured with 33MHz clock source on XTAL1, V
4. Stop mode current measured with XTAL1 and RST grounded, V
5. When addressing external memory.
6. RST=V
7. During a 0 to 1 transition, a one-shot drives the ports hard for two oscillator clock cycles. This
8. Ports 1, 2, 3, 5, 6 source transition current when being pulled down externally. Current reaches its
9. 0.45<V
10. 0.45< V
11. This is the current required from an external circuit to hold a logic low level on an I/O pin while the
disconnected.
pins disconnected.
This value is not guaranteed. Users that are sensitive to this specification should contact Dallas
Semiconductor for more information.
at a logic high state during I/O mode.
measurement reflects port in transition mode.
maximum at approximately 2V.
Peak current occurs near the input transition point of the latch, approximately 2V.
corresponding port latch is set to 1. This is only the current required to hold the low level; transitions
from 1 to 0 on an I/O pin will also have to overcome the transition current.
IN
CC
IN
<V
. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when
<V
CC
CC
. Not a high-impedance input. This port is a weak address holding latch in Bus Mode.
. RST=V
CC
. This condition mimics operation of pins in I/O mode.
35 of 49
CC
=5.5V, all other pins disconnected.
CC
=5.5V, RST at ground, other
CC
=RST=5.5V, other pins