SAF-TC1130-L100EB BB Infineon Technologies, SAF-TC1130-L100EB BB Datasheet - Page 21

• Manufacturer Part Number: SAF-TC1130-L100EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L100EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L100EBBBNP; SAFTC1130L100EBBB; SP000099810

Table 2-1
Symbol
TRST
TCK
TDI
TDO
TMS
TRCLK
HWCFG0
HWCFG1
HWCFG2
BRKIN
MII_
TXCLK
MII_
RXCLK
MII_
MDIO
D+
Data Sheet
Pin
T11
T12
T13
T10
T9
T8
M14
L14
T6
T5
T2
R2
R1
T14
Pin Definitions and Functions (cont’d)
In
Out
I
I
I
O
I
O
I
I
I
I
I
I
I/O
I/O
PU/
PD
PDC JTAG Module Reset/Enable Input
PUC JTAG Module Clock Input
PUC JTAG Module Serial Data Input
⎯
PUC JTAG Module State Machine Control Input
⎯
PUC
PUC
PDC
PUC OCDS Break Input
PDC Ethernet Controller Transmit Clock
PDC Ethernet Controller Receive Clock
PDA
⎯
1)
Functions
A low level at this pin resets and disables the JTAG
module. A high level enables the JTAG module.
JTAG Module Serial Data Output
Trace Clock for OCDS_L2 Lines
Hardware Configuration Inputs
The Configuration Inputs define the boot options of the
TC1130 after a hardware invoked reset operation.
A low level on this pin causes a break in the chip’s
execution when the OCDS is enabled. In addition, the
level of this pin during power-on reset determines the
boot configuration.
MII_TXD[3:0] and MII_TXEN are driven off the rising
edge of the MII_TXCLK by the core and sampled by
the PHY on the rising edge of the MII_TXCLK.
MII_RXCLK is a continuous clock. Its frequency is
25 MHz for 100 Mbit/sec operation, and 2.5 MHz for
10 Mbit/sec. MII_RXD[3:0], MII_RXDV and MII_EXER
are driven by the PHY off the falling edge of
MII_RXCLK and sampled on the rising edge of
MII_RXCLK.
Ethernet Controller Management Data Input/
Output
When a read command is being executed, the data
that is clocked out of the PHY will be presented on the
input line. When the Core is clocking control or data
onto the MII_MDIO line, the signal will carry the
information.
USB D+ Data Line
15
General Device Information
V1.1, 2008-12
TC1130