SAF-TC1130-L100EB BB Infineon Technologies, SAF-TC1130-L100EB BB Datasheet - Page 70

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SAF-TC1130-L100EB BB

Manufacturer Part Number
SAF-TC1130-L100EB BB
Description
IC MCU 32BIT TRICOR 16KB LBGA208
Manufacturer
Infineon Technologies
Series
TC11xxr
Datasheet

Specifications of SAF-TC1130-L100EB BB

Core Processor
TriCore
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Type
ROMless
Ram Size
144K x 8
Voltage - Supply (vcc/vdd)
1.43 V ~ 1.58 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LSBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
FT1130L100EBBBNP
SAFTC1130L100EBBB
SP000099810
3.22
The TC1130 power management system allows software to configure the various
processing units to adjust automatically in order to draw the minimum necessary power
for the application.
There are four power management modes:
• Run Mode
• Idle Mode
• Sleep Mode
• Deep Sleep Mode
Table 3-4
Table 3-4
Mode
Run
Idle
Sleep
Deep Sleep
Besides these explicit software-controlled power-saving modes, special attention has
been paid in the TC1130 to automatic power-saving in operating units that are currently
not required or idle. In this case, they are shut off automatically until their operation is
required again.
Data Sheet
describes the features of the power management modes.
Power Management System
Power Management Mode Summary
Description
The system is fully operational. All clocks and peripherals are enabled,
as determined by software.
The CPU clock is disabled, waiting for a condition to return it to run mode.
Idle mode can be entered by software when the processor has no active
tasks to perform. All peripherals remain powered and clocked. Processor
memory is accessible to peripherals. A reset, Watchdog Timer event, a
falling edge on the NMI pin, or any enabled interrupt event will return the
system to run mode.
The system clock continues to be distributed only to those peripherals
programmed to operate in sleep mode. The other peripheral modules will
be shut down by the suspend signal. Interrupts from operating
peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset
event will return the system to run mode. Entering this state requires an
orderly shut-down controlled by the Power Management State Machine.
The system clock is shut off; only an external signal will restart the
system. Entering this state requires an orderly shut-down controlled by
the Power Management State Machine (PMSM).
64
Functional Description
V1.1, 2008-12
TC1130

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