LT1168CS8#PBF Linear Technology, LT1168CS8#PBF Datasheet - Page 11

• Manufacturer Part Number: LT1168CS8#PBF
• Description: IC AMP INSTR PREC PROG 8-SOIC
• Manufacturer: Linear Technology
• Type: Instrumentation Ampr

Specifications of LT1168CS8#PBF

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Slew Rate: 0.5 V/µs
• Gain Bandwidth Product: 400kHz
• Current - Input Bias: 80pA
• Voltage - Input Offset: 20µV
• Current - Supply: 350µA
• Current - Output / Channel: 32mA
• Voltage - Supply, Single/dual (±): 4.6 V ~ 36 V, ±2.3 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Channels: 1
• Number Of Elements: 1
• Power Supply Requirement: Dual
• Common Mode Rejection Ratio: 85dB
• Input Resistance: 1250000@±15VMohm
• Input Offset Voltage: 0.06@±15VmV
• Input Bias Current: 0.0005@±15VnA
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): 15V
• Power Supply Rejection Ratio: 100dB
• Rail/rail I/o Type: No
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±2.3V
• Dual Supply Voltage (max): ±18V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Compliant

BLOCK DIAGRA
THEORY OF OPERATIO
The LT1168 is a modified version of the three op amp
instrumentation amplifier. Laser trimming and monolithic
construction allow tight matching and tracking of circuit
parameters over the specified temperature range. Refer to
the block diagram (Figure 1) to understand the following
circuit description. The collector currents in Q1 and Q2 are
trimmed to minimize offset voltage drift, thus assuring a
high level of performance. R1 and R2 are trimmed to an
absolute value of 24.7k to assure that the gain can be set
accurately (0.6% at G = 100) with only one external
resistor R
determines the transconductance of the preamp stage. As
R
ductance of the input preamp stage increases to that of the
input transistors Q1 and Q2. This increases the open-loop
gain when the programmed gain is increased, reducing
the input referred gain related errors and noise. The input
G
is reduced for larger programmed gains, the transcon-
G
. The value of R
–IN
+IN
R
R
G
G
2
1
8
3
–V
–V
S
S
400Ω
400Ω
W
R3
R4
G
+V
+V
S
S
in parallel with R1 (R2)
U
Q1
Q2
PREAMP STAGE
VB
VB
Figure 1. Block Diagram
–
+
+
–
24.7k
24.7k
R1
R2
A1
A2
C1
C2
voltage noise at gains greater than 50 is determined only
by Q1 and Q2. At lower gains the noise of the difference
amplifier and preamp gain setting resistors increase the
noise. The gain bandwidth product is determined by C1,
C2 and the preamp transconductance which increases
with programmed gain. Therefore, the bandwidth does not
drop proportionally with gain.
The input transistors Q1 and Q2 offer excellent matching,
which is inherent in NPN bipolar transistors, as well as
picoampere input bias current due to superbeta process-
ing. The collector currents in Q1 and Q2 are held constant
due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop which in turn impresses the differential
input voltage across the external gain set resistor R
Since the current that flows through R
R1 and R2, the ratios provide a gained-up differential
30k
30k
R5
R7
DIFFERENCE AMPLIFIER STAGE
–
+
A3
30k
30k
R6
R8
–V
–V
S
S
6
5
7
4 –V
1168 F01
G
+V
OUTPUT
REF
also flows through
S
S
LT1168
11
1168fa
G
.