LT1167ACS8#PBF Linear Technology, LT1167ACS8#PBF Datasheet - Page 12
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LT1167ACS8#PBF
Manufacturer Part Number
LT1167ACS8#PBF
Description
IC PREC INSTRMNT-AMP PROG 8-SOIC
Manufacturer
Linear Technology
Specifications of LT1167ACS8#PBF
Amplifier Type
Instrumentation
Number Of Circuits
1
Slew Rate
1.2 V/µs
Gain Bandwidth Product
1MHz
Current - Input Bias
50pA
Voltage - Input Offset
15µV
Current - Supply
900µA
Current - Output / Channel
27mA
Voltage - Supply, Single/dual (±)
4.6 V ~ 36 V, ±2.3 V ~ 18 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
No. Of Amplifiers
1
Input Offset Voltage
15µV
Gain Db Min
1dB
Gain Db Max
10000dB
Bandwidth
1000kHz
Amplifier Output
Single Ended
Cmrr
140dB
Supply Voltage Range
± 2.3V To
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Type
-
-3db Bandwidth
-
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LT1167
THEORY OF OPERATIO
Input and Output Offset Voltage
The offset voltage of the LT1167 has two components: the
output offset and the input offset. The total offset voltage
referred to the input (RTI) is found by dividing the output
offset by the programmed gain (G) and adding it to the
input offset. At high gains the input offset voltage domi-
nates, whereas at low gains the output offset voltage
dominates. The total offset voltage is:
Reference Terminal
The reference terminal is one end of one of the four 10k
resistors around the difference amplifier. The output volt-
age of the LT1167 (Pin 6) is referenced to the voltage on
the reference terminal (Pin 5). Resistance in series with
the REF pin must be minimized for best common mode
rejection. For example, a 2 resistance from the REF pin
to ground will not only increase the gain error by 0.02%
but will lower the CMRR to 80dB.
Single Supply Operation
For single supply operation, the REF pin can be at the same
potential as the negative supply (Pin 4) provided the
output of the instrumentation amplifier remains inside the
specified operating range and that one of the inputs is at
least 2.5V above ground. The barometer application on the
front page of this data sheet is an example that satisfies
these conditions. The resistance R
ducer to ground sets the operating current for the bridge
and also has the effect of raising the input common mode
voltage. The output of the LT1167 is always inside the
specified range since the barometric pressure rarely goes
low enough to cause the output to rail (30.00 inches of Hg
corresponds to 3.000V). For applications that require the
output to swing at or below the REF potential, the voltage
on the REF pin can be level shifted. An op amp is used to
buffer the voltage on the REF pin since a parasitic series
resistance will degrade the CMRR. The application in the
back of this data sheet, Four Digit Pressure Sensor, is an
example.
12
Total input offset voltage (RTI)
= input offset + (output offset/G)
Total output offset voltage (RTO)
= (input offset • G) + output offset
b
from the bridge trans-
U
Output Offset Trimming
The LT1167 is laser trimmed for low offset voltage so that
no external offset trimming is required for most applica-
tions. In the event that the offset needs to be adjusted, the
circuit in Figure 2 is an example of an optional offset adjust
circuit. The op amp buffer provides a low impedance to the
REF pin where resistance must be kept to minimum for
best CMRR and lowest gain error.
Input Bias Current Return Path
The low input bias current of the LT1167 (350pA) and the
high input impedance (200G ) allow the use of high
impedance sources without introducing additional offset
voltage errors, even when the full common mode range is
required. However, a path must be provided for the input
bias currents of both inputs when a purely differential
signal is being amplified. Without this path the inputs will
float to either rail and exceed the input common mode
range of the LT1167, resulting in a saturated input stage.
Figure 3 shows three examples of an input bias current
path. The first example is of a purely differential signal
source with a 10k input current path to ground. Since the
impedance of the signal source is low, only one resistor is
needed. Two matching resistors are needed for higher
impedance signal sources as shown in the second
example. Balancing the input impedance improves both
common mode rejection and DC offset. The need for input
resistors is eliminated if a center tap is present as shown
in the third example.
–IN
+IN
Figure 2. Optional Trimming of Output Offset Voltage
R
G
2
1
8
3
–
+
LT1167
ADJUSTMENT RANGE
REF
5
10mV
1
6
LT1112
1/2
OUTPUT
+
–
2
3
10k
V
V
+
–
10mV
100
100
–10mV
1167 F02