AD8556ARZ Analog Devices Inc, AD8556ARZ Datasheet - Page 16

• Manufacturer Part Number: AD8556ARZ
• Description: IC AMP CHOPPER 2MHZ 10MA 8SOIC
• Manufacturer: Analog Devices Inc
• Series: DigiTrim®r
• Type: Instrumentation Amplifierr

Specifications of AD8556ARZ

• Operating Temperature: -40°C ~ 140°C
• Amplifier Type: Chopper (Zero-Drift)
• Number Of Circuits: 1
• Slew Rate: 1.2 V/µs
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 49nA
• Voltage - Input Offset: 2µV
• Current - Supply: 2mA
• Current - Output / Channel: 10mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Bandwidth: 700kHz
• Rail To Rail I/o Type: Rail-Rail I/O
• No. Of Channels: 1
• Supply Voltage Range: 2.7V To 5.5V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Number Of Channels: 1
• Number Of Elements: 5
• Power Supply Requirement: Single
• Common Mode Rejection Ratio: 80dB
• Unity Gain Bandwidth Product (typ): 8MHz
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Rejection Ratio: 109dB
• Rail/rail I/o Type: Rail to Rail Input/Output
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 140C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Compliant

AD8556
THEORY OF OPERATION
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiometers,
guaranteed to be monotonic. Programming P1 and P2 allows
the first stage gain to be varied from 4.0 to 6.4 with 7-bit
resolution (see Table 5 and Equation 1), giving a fine gain
adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each
have a similar temperature coefficient; therefore, the first stage
gain temperature coefficient is lower than 100 ppm/°C.
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of
the differential amplifier. A3 is also an auto-zeroed op amp that
minimizes input offset errors. P3 and P4 are digital potentiometers
that allow the second stage gain to be varied from 17.5 to 200 in
eight steps (see Table 6). R4, R5, R6, R7, P3, and P4 each have a
similar temperature coefficient; therefore, the second stage gain
temperature coefficient is lower than 100 ppm/°C.
RF together with an external capacitor, connected between
FILT/DIGOUT and VSS or VDD, form a low-pass filter. The
filtered signal is buffered by A4 to give a low impedance output
at VOUT. RF is nominally 18 kΩ, allowing an 880 Hz low-pass
filter to be implemented by connecting a 10 nF external capacitor
between FILT/DIGOUT and VSS or between FILT/DIGOUT
and VDD. If low-pass filtering is not needed, the FILT/DIGOUT
pin must be left floating.
A5 implements a voltage buffer that provides the positive supply
to A4, the amplifier output buffer. Its function is to limit VOUT
to a maximum value, useful for driving ADCs operating on
supply voltages lower than VDD. The input to A5, VCLAMP,
has a very high input resistance. It should be connected to a
known voltage and not left floating. However, the high input
impedance allows the clamp voltage to be set using a high
impedance source, such as a potential divider. If the maximum
value of VOUT does not need to be limited, VCLAMP should
be connected to VDD.
GAIN1
≈
4
×
⎛
⎜
⎝
6.4
4
⎞
⎟
⎠
⎛
⎜
⎝
Code
127
⎞
⎟
⎠
Rev. A | Page 16 of 28
(1)
A4 implements a rail-to-rail input and output unity-gain
voltage buffer. The output stage of A4 is supplied from a
buffered version of VCLAMP instead of VDD, allowing the
positive swing to be limited. The maximum output current is
limited between 5 mA to 10 mA.
An 8-bit DAC is used to generate a variable offset for the
amplifier output. This DAC is guaranteed to be monotonic.
To preserve the ratiometric nature of the input signal, the DAC
references are driven from VSS and VDD, and the DAC output
can swing from VSS (Code 0) to VDD (Code 255). The 8-bit
resolution is equivalent to 0.39% of the difference between
VDD and VSS, for example, 19.5 mV with a 5 V supply. The
DAC output voltage (VDAC) is given approximately by
where the temperature coefficient of VDAC is lower than
200 ppm/°C.
The amplifier output voltage (VOUT) is given by
where GAIN is the product of the first and second stage gains.
VNEG
VPOS
VOUT = GAIN ( VPOS − VNEG ) + VDAC
VDAC
A1
A2
VDD
VSS
VDD
VSS
≈
⎛
⎜
⎝
Code
R1
R3
R2
VDD
DAC
VSS
P1
P2
Figure 47. Functional Schematic
256
R4
R5
+
0.5
P4
P3
⎞
⎟
⎠
(
VDD
A3
VDD
VSS
R6
R7
−
VCLAMP
VSS
RF
DIGOUT
)
FILT/
+
VSS
A5
VDD
VSS
VDD
A4
VSS
VOUT
(2)
(3)