AD824AR-14 Analog Devices Inc, AD824AR-14 Datasheet - Page 11

• Manufacturer Part Number: AD824AR-14
• Description: IC OPAMP JFET R-R 2MHZ LP 14SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD824AR-14

• Slew Rate: 2 V/µs
• Rohs Status: RoHS non-compliant
• Amplifier Type: J-FET
• Number Of Circuits: 4
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 2MHz
• -3db Bandwidth: 2MHz
• Current - Input Bias: 4pA
• Voltage - Input Offset: 500µV
• Current - Supply: 560µA
• Current - Output / Channel: 12mA
• Voltage - Supply, Single/dual (±): 3 V ~ 30 V, ±1.5 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Op Amp Type: Low Power
• No. Of Amplifiers: 4
• Bandwidth: 2MHz
• Supply Voltage Range: 3V To 30V
• Amplifier Case Style: SOIC
• No. Of Pins: 14
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –V
than +V
cause a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages
up to and including +V
AD824 voltage follower to a 0 V to 5 V (+V
The input and output are superimposed. The output tracks the
input up to +V
above a 4 V input causes the rounding of the output wave form.
For input voltages greater than +V
the AD824’s noninverting input will prevent phase reversal at
the expense of greater input voltage noise. This is illustrated in
Figure 2b.
Figure 2. (a) Response with R
Since the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +V
internal device junctions become forward biased. This is
illustrated in TPC 8.
REV. C
S
S
. Driving the input voltage closer to the positive rail will
– 0.4 V, the input current will reverse direction as
(b) V
GND
GND
+V
V
R
S
S
OUT
P
V
IN
without phase reversal. The reduced bandwidth
100
100
0%
IN
0%
90
90
10
10
= 49.9 k W
= 0 to + V
= 0 to + V
1V
1V
1V
1V
S
. Figure 2a shows the response of an
R
P
1V
S
S
+ 200 m V
P
(a)
(b)
+5V
= 0; V
S
2µs
, a resistor in series with
IN
from 0 to +V
10µs
S
) square wave input.
V
OUT
S
to 1 V less
S
–11–
A current-limiting resistor should be used in series with the
input of the AD824 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV or if an
input voltage will be applied to the AD824 when ± V
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kW resistor allows the amplifier to withstand up
to 10 V of continuous overvoltage and increases the input volt-
age noise by a negligible amount.
Input voltages less than –V
The amplifier can safely withstand input voltages 20 V below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 V. In addition,
the input stage typically maintains picoamp level input currents
across that input voltage range.
OUTPUT CHARACTERISTICS
The AD824’s unique bipolar rail-to-rail output stage swings
within 15 mV of the positive and negative supply voltages. The
AD824’s approximate output saturation resistance is 100 W for
both sourcing and sinking. This can be used to estimate output
saturation voltage when driving heavier current loads. For
instance, the saturation voltage will be 0.5 V from either supply
with a 5 mA current load.
For load resistances over 20 kW, the AD824’s input error
voltage is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
If the AD824’s output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2 ms of its
input returning to the amplifier’s linear operating region.
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. TPC 4 and 6 show the AD824’s
pulse response as a unity gain follower driving 220 pF. Configu-
rations with less loop gain, and as a result less loop bandwidth,
will be much less sensitive to capacitance load effects. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
Figure 3 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component val-
ues, the circuit will drive 5,000 pF with a 10% overshoot.
Figure 3. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
V
IN
AD824
8
1/4
4
20k
+V
–V
S
S
0.01 F
0.01 F
S
20pF
are a completely different story.
100
C
L
AD824
V
OUT
S
= 0. The