CLC5523IM National Semiconductor, CLC5523IM Datasheet - Page 11

• Manufacturer Part Number: CLC5523IM
• Description: IC AMP VARIABLE GAIN 8-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC5523IM

• Amplifier Type: Variable Gain
• Number Of Circuits: 1
• Slew Rate: 1800 V/µs
• -3db Bandwidth: 250MHz
• Current - Input Bias: 3µA
• Current - Supply: 13.5mA
• Current - Output / Channel: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Voltage - Supply, Single/dual (±): -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Other names: *CLC5523IM

Application Division
difference in output levels when V
Capacitance coupling through the board and package as
well as coupling through the supplies will determine the
amount of feedthrough. Even at DC, the input signal will not
be completely rejected. At high frequencies feedthrough will
get worse because of its capacitive nature. At low frequen-
cies, the feedthrough will be 80dB below the maximum gain,
and therefore it can be said that the CLC5523 has an 80dB
Gain Control Range.
CLC5523 Gain Control Function
In the two plots, Gain vs. V
function of the control voltage. The first plot, sometimes
referred to as the S-curve, is the linear (V/V) gain. This is a
hyperbolic tangent relationship. The second gain curve plots
the gain in dB and is linear over a wide range of gains.
Because of this, the CLC5523 gain control is referred to as
“linear-in-dB.”
For applications where the CLC5523 will be used at the
heart of a closed loop AGC circuit, the S-curve control char-
acteristic provides a broad linear (in dB) control range with
soft limiting at the highest gains where large changes in
control voltage result in small changes in gain. For applica-
tions, requiring a fully linear (in dB) control characteristic,
use the CLC5523 at half gain and below (V
Avoiding Overdrive of the CLC5523 Gain Control Input
There is an additional requirement for the CLC5523 Gain
Control Input (V
trol circuitry may saturate and the gain may actually be
reduced. In applications where V
DAC, this can easily be addressed in the software. If there is
a linear loop driving V
of limiting the input voltage should be implemented. One
simple solution is to place a 2:1 resistive divider on the V
input. If the device driving this divider is operating off of
supplies as well, its output will not exceed 5V and through
the divider V
Improving the CLC5523 Large Signal Performance
Figure 2 illustrates an inverting gain scheme for the
CLC5523.
The input signal is applied through the R
pin should be grounded through a 25
mum gain range of this configuration is given in the following
equation:
25
FIGURE 2. Inverting the CLC5523
g
V
can not exceed 2.5V.
in
g
):V
R
g
must not exceed +2.5V. The gain con-
g
g
, such as an AGC loop, other methods
25
2
3
CLC5523
V
g
G
1
4
, we can see the gain as a
g
g
= 2V and when V
(Continued)
is being driven from a
7
6
resistor. The maxi-
R
g
f
resistor. The V
g
1V)
DS012798-33
V
g
= OV.
o
±
5V
in
g
11
The inverting slew rate of the CLC5523 is much higher than
that of the non-inverting slew rate. This 2.5X performance
improvement comes about because in the non-inverting con-
figuration, the slew rate of the overall amplifier is limited by
the input buffer. In the inverting circuit, the input buffer re-
mains at a fixed voltage and does not affect slew rate.
Transmission Line Matching
One method for matching the characteristic impedance of a
transmission line is to place the appropriate resistor at the
input or output of the amplifier. Figure 3 shows a typical
circuit configuration for matching transmission lines.
The resistors R
istic impedance, Z
to match the output transmission line over a greater fre-
quency range. It compensates for the increase of the op
amp’s output impedance with frequency.
Minimizing Parasitic Effects on Small Signal Bandwidth
The best way to minimize parasitic effects is to use the small
outline package and surface mount components. For de-
signs utilizing through-hole components, specifically axial
resistors, resistor self-capacitance should be considered.
Example: the average magnitude of parasitic capacitance of
RN55D 1% metal film resistors is about 0.15pF with varia-
tions of as much as 0.1pF between lots. Given the
CLC5523’s extended bandwidth, these small parasitic reac-
tance variations can cause measurable frequency response
variations in the highest octave. We therefore recommend
the use of surface mount resistors to minimize these para-
sitic reactance effects. If an axial component is preferred, we
recommend PRP8351 resistors which are available from
Precision Resistive Products, Inc., Highway 61 South, Me-
diapolis, Iowa.
Small Signal Response at Low A
When the maximum gain, as set by R
than or equal to A
observed in the amplifier response. When the gain range is
set to less than A
at higher frequencies. At gain ranges of 2 A
reaches approximately 6dB in the upper octave.
If peaking is observed with the recommended R
and a small increase in the R
problem, then investigate the possible causes and remedies
listed below.
• Capacitance across R
•
Do not place a capacitor across R
FIGURE 3. Transmission Line Matching
s
, R
vmax
o
, of the transmission line or cable. Use C
vmax
i
,R
= 10, some peaking may be observed
o
, and R
=10, little or no peaking should be
f
T
f
resistor does not solve the
are equal to the character-
vmax
g
f
and R
vmax
<
f
www.national.com
, is greater
2 peaking
f
DS012798-35
resistor,
o