CLC5523IM National Semiconductor, CLC5523IM Datasheet - Page 12

• Manufacturer Part Number: CLC5523IM
• Description: IC AMP VARIABLE GAIN 8-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC5523IM

• Amplifier Type: Variable Gain
• Number Of Circuits: 1
• Slew Rate: 1800 V/µs
• -3db Bandwidth: 250MHz
• Current - Input Bias: 3µA
• Current - Supply: 13.5mA
• Current - Output / Channel: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Voltage - Supply, Single/dual (±): -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Other names: *CLC5523IM

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Application Division
Adjusting Offsets and DC Level Shifting
Offsets can be broken into two parts: an input-referred term
and an output-referred term. These errors can be trimmed
using the circuit in Figure 4 . First set V
trim pot R4 to null the offset voltage at the output. This will
eliminate the output stage offsets. Next set V
adjust the trim pot R1 to null the offset voltage at the output.
This will eliminate the input stage offsets.
Printed Circuit Board Layout
High frequency op amp performance is strongly dependent
on proper layout, proper resistive termination and adequate
power supply decoupling. The most important layout points
to follow are:
•
• Capacitive Loads
•
• Long traces and/or lead lengths between R
•
• Long traces between CLC5523 and 0.1µF bypass ca-
•
•
• Extra capacitance between the R
•
•
• Non-inverting input pin connected directly to ground
•
• Use a ground plane
• Bypass each power supply pin with these capacitors:
•
•
possible
and C
CLC5523
pacitors
1000pF monolithic capacitor should be placed less than
0.1” (3mm) from the pin
(C
low for suggestions on reducing C
C
pin and ground
0.2” (5mm) from the pin
the pin
g
Keep traces connecting R
Place a small resistor (20-50 ) between the output
Keep these traces as short as possible
Keep these traces less than 0.2 inches (5mm)
For the devices in the PDIP package, an additional
See the Printed Circuit Board Layout sub-section be-
Increase R
Place a 50 to 200
a high-quality 0.1µF ceramic capacitor placed less than
a 6.8µF tantalum capacitor less than 2” (50mm) from
g
)
L
FIGURE 4. Offset Adjust Circuit
f
if peaking is still observed after reducing
resistor between the non-inverting
f
separated and as short as
(Continued)
G
g
to OV and adjust the
g
pin and ground
g
DS012798-36
to 2V and
f
and the
12
•
Capacitively bypassing power pins to a good ground plane
with a minimum of trace length (inductance) is necessary for
any high speed device, but it is particularly important for the
CLC5523.
• Establish wide, low impedance, power supply traces
• For the plastic DIP package, a 25
• Minimize or eliminate source of capacitance between the
• Minimize trace and lead lengths for components between
•
•
To minimize high frequency distortion, other layout issues
need be addressed.
• Short, equal length, low impedance power supply return
• avoid returning output ground currents near the input
Evaluation Boards
Evaluation boards are available for both the 8-pin DIP and
small outline package types. Free evaluation boards are
shipped when a device sample request is placed with Na-
tional Semiconductor. The 8-pin DIP evaluation kit part num-
ber is CLC730065. The 8-pin small outline evaluation kit part
number is CLC730066.
The DIP evaluation kit has been designed to utilize axial lead
components. The small outline evaluation kit has been de-
signed to utilize surface mount components.
The circuit diagram shown in Figure 5 , applies to both the
DIP and the small outline evaluation boards.
ceramic capacitor placed less than 0.1” (3mm) from the
pin
connected from pin 4 to ground with a minimum length
trace
R
vias between the R
ometry may give rise to a significant source of capaci-
tance.
the inverting and output pins
pads
board pins; never use high profile DIP sockets
paths from the load to the supplies
stage
f
for the plastic DIP package, a high-quality 1000pF
Remove ground plane 0.1” (3mm) from all input/output
For prototyping, use flush-mounted printed circuit
pin and the output pin. Avoid adjacent feedthrough
FIGURE 5. Evaluation Board Schematic
f
and output leads since such a ge-
resistor should be
DS012798-37