LTC693CSW Linear Technology, LTC693CSW Datasheet - Page 11

• Manufacturer Part Number: LTC693CSW
• Description: IC MPU SUPERVISRY CIRCUIT 16SOIC
• Manufacturer: Linear Technology
• Type: Simple Reset/Power-On Resetr

Specifications of LTC693CSW

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC693CS

Memory Protection
The LTC693 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when V
ditional pins, CE IN and CE OUT, control the Chip Enable
or Write inputs of CMOS RAM. When V
follows CE IN with a typical propagation delay of 20ns.
When V
CE OUT is forced high, independent of CE IN. CE OUT is
an alternative signal to drive the CE, CS, or Write input of
APPLICATIONS INFORMATION
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond V
to the lead inductance (Figure 4).
Table 1 shows the state of each pin during battery backup.
When the battery switchover section is not used, connect
V
BATT
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
to GND and V
CC
falls below the reset voltage threshold or V
CE OUT
10Ω
CE IN
V
CC
OUT
V
OUT
to V
3.9M
CC
= V
BATT
is at an invalid level. Two ad-
CC
.
0.1μF
Figure 5. Timing Diagram for CE IN and CE OUT
V
BATT
CC
LTC692
LTC693
GND
is 5V, CE OUT
692_3 • F04
CC
V1
BATT
due
,
V2
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM
or NOVRAM to achieve similar protection. Figure 5 shows
the timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
Memory protection can also be achieved with the LTC692
by using RESET as shown in Figure 7.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL
V
V
V
BATT ON
PFI
PFO
RESET
RESET
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
CC
OUT
BATT
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
STATUS
C2 monitors V
V
The supply current is 1μA maximum
Logic high. The open-circuit output voltage is equal to V
Power failure input is ignored
Logic low
Logic low
Logic high. The open-circuit output voltage is equal to V
Watchdog input is ignored
Logic high. The open-circuit output voltage is equal to V
Chip Enable input is ignored
Logic high. The open-circuit output voltage is equal to V
OSC IN is ignored
OSC SEL is ignored
OUT
is connected to V
CC
for active switchover
LTC692/LTC693
BATT
through an internal PMOS switch
692_3 • F05
V
OUT
= V
BATT
11
OUT
OUT
OUT
OUT
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