LTC693CSW Linear Technology, LTC693CSW Datasheet - Page 7

• Manufacturer Part Number: LTC693CSW
• Description: IC MPU SUPERVISRY CIRCUIT 16SOIC
• Manufacturer: Linear Technology
• Type: Simple Reset/Power-On Resetr

Specifications of LTC693CSW

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC693CS

PIN FUNCTIONS
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when V
V
drive for an external PNP transistor to increase the output
current above the 50mA rating of V
when V
CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CE OUT : Logic Output on the Chip Enable Gating Circuit.
When V
a buffered replica of CE IN. When V
voltage threshold CE OUT is forced high (see Figure 5).
GND: Ground Pin.
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the V
falls below the reset voltage threshold (4.40V typically),
LOW LINE goes low. As soon as V
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V
Table 1).
OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or an external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this confi guration the nominal reset active
time and watchdog timeout period are determined by the
number of clocks or set by the formula (see Applications
Information section). When OSC SEL is high or fl oating,
the internal oscillator is enabled and the reset active time
is fi xed at 200ms typical. OSC IN selects between the 1.6
seconds and 100ms typical watchdog timeout periods. In
both cases the timeout period immediately after a reset is
1.6 seconds typical.
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or fl oating, the internal oscillator sets the reset active
time and watchdog timeout period. Forcing OSC SEL low
allows OSC IN to be driven from an external clock signal
or an external capacitor to be connected between OSC
IN and GND.
CC
. The output typically sinks 35mA and can provide base
OUT
CC
is above the reset voltage threshold, CE OUT is
is internally switched to V
OUT
CC
is internally connected to
drops below V
CC
OUT
CC
rises above the reset
. BATT ON goes high
CC
BATT
is below the reset
input. When V
.
BATT
(see
CC
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes
low when PFI is below 1.3V. Connect PFI to GND or V
when C3 is not used.
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When V
PFO is forced low.
RESET: Logic Output for μP Reset Control. Whenever V
falls below either the reset voltage threshold (4.40V typi-
cally) or V
to 5V, reset pulse generator forces RESET to remain active
low for a minimum of 140ms. When the watchdog timer is
enabled but not serviced prior to a preset timeout period,
reset pulse generator also forces RESET to active low for
a minimum of 140ms for every preset timeout period
(see Figure 11). The reset active time is adjustable on
the LTC693. An external pushbutton reset can be used in
connection with the RESET output. See Pushbutton Reset
in the Applications Information section.
RESET: RESET is an Active High Logic Output. It is the
inverse of RESET.
V
auxiliary power connected to V
through PMOS switch, M2. If backup battery or auxiliary
power is not used, V
V
with a 0.1μF capacitor.
V
a capacitor of 0.1μF or greater. During normal operation,
V
switch, M1, which can deliver up to 50mA and has a typical
on-resistance of 5Ω. When V
is internally switched to V
used, connect V
BATT
CC
OUT
OUT
: 5V Supply Input. The V
: Voltage Output for Backed-Up Memory. Bypass with
: Backup Battery Input. When V
obtains power from V
BATT
CC
, RESET goes active low. After V
is lower than V
OUT
to V
BATT
CC
LTC692/LTC693
should be connected to GND.
BATT
.
CC
CC
CC
. If V
BATT
through an NMOS power
BATT
is lower than V
pin should be bypassed
OUT
, C3 is shut down and
CC
is delivered to V
and V
falls below V
BATT
CC
BATT
returns
are not
, V
BATT
0692fb
7
OUT
OUT
OUT
CC
,