ISL9012IRPLZ Intersil, ISL9012IRPLZ Datasheet - Page 8

• Manufacturer Part Number: ISL9012IRPLZ
• Description: IC LDO HI PSRR 1.85/2.9V 10-DFN
• Manufacturer: Intersil

Specifications of ISL9012IRPLZ

• Regulator Topology: Positive Fixed
• Voltage - Output: 1.85V, 2.9V
• Voltage - Input: 2.3 ~ 6.5 V
• Voltage - Dropout (typical): -, 0.2V @ 300mA
• Number Of Regulators: 2
• Current - Output: 150mA (Max), 300mA (Max)
• Current - Limit (min): 350mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
Typical Application
NUMBER
PIN
10
1
2
3
4
5
6
7
8
9
VIN (2.3V TO 6.5V)
ENABLE 1
ENABLE 2
NAME
CPOR
CBYP
GND
POR
EN1
EN2
VO2
VO1
PIN
VIN
NC
OFF
OFF
Analog I/O
Low Voltage Compatible
CMOS Input
Low Voltage Compatible
CMOS Input
Analog I/O
Analog I/O
Ground
NC
Open Drain Output (1mA)
Analog I/O
Analog I/O
ON
ON
8
C1
TYPE
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X5R CERAMIC CAPACITOR
C3: 0.01µF X5R CERAMIC CAPACITOR
R1: 100kΩ RESISTOR, 5%
C2
C3
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
LDO-1 Enable.
LDO-2 Enable.
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
POR Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR output release after LDO-2
output reaches 94% of its specified voltage level (200ms delay per 0.01µF).
GND is the connection to system ground. Connect to PCB Ground plane.
No Connection.
Open-drain POR Output for LDO-2 (active-low).
LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
1
2
3
4
5
VIN
EN1
EN2
CBYP
CPOR
ISL9012
ISL9012
GND
POR
VO1
VO2
NC
10
9
8
7
6
C4
C5
DESCRIPTION
R1
V
OUT
V
2 TOO LOW
OUT
2 OK
V
V
RESET
(200ms DELAY, C3 = 0.01µF)
OUT
OUT
2
1
March 11, 2008
FN9220.3