XC56309VF100A Freescale Semiconductor, XC56309VF100A Datasheet - Page 116

• Manufacturer Part Number: XC56309VF100A
• Description: IC DSP 24BIT FIXED-POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VF100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Host Interface (HI08)
6.6.6 Host Port Control Register (HPCR)
The HPCR is a read/write control register that controls the HI08 operating mode. HPCR bit
initialization values are discussed in Section 6.6.9, DSP-Side Registers After Reset, on page
6-20. Hardware and software reset clear the HPCR bits.
To assure proper operation of the DSP56309, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX,
HASP, HDSP, HROD, HAEN, and HREN should be changed only if HEN is cleared. Similarly,
the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN,
HCSEN, HA9EN, and HA8EN should not be set when HEN is set nor at the time HEN is set.
6-16
Bit Number
HAP
15
15
14
—Reserved bit, read as 0; write to 0 for future compatibility.
HRP HCSP HDDS HMUX HASP HDSP HROD
14
Bit Name
13
Figure 6-12. Host Port Control Register (HPCR) (X:$FFFFC4)
Table 6-12. Host Port Control Register (HPCR) Bit Definitions
HRP
HAP
DSP Peripheral
12
HAD[0–7]
HA[8–10]
Data Bus
Reset Value
11
HAS
Figure 6-11. Self Chip-Select Logic
0
0
10
DSP56309 User’s Manual, Rev. 1
Host Acknowledge Polarity
If HAP is cleared, the host acknowledge (HACK) signal is configured as an
active low input. The HI08 drives the contents of the IVR onto the host bus
when the HACK signal is low. If the HAP bit is set, the HACK signal is
configured as an active high input. The HI08 outputs the contents of the IVR
when the HACK signal is high.
Host Request Polarity
Controls the polarity of the host request signals. In single host request mode
(that is, when HDRQ is cleared in the ICR), if HRP is cleared and host
requests are enabled (that is, if HREN is set and HEN is set), then the HREQ
signal is an active low output. If HRP is set and host requests are enabled,
the HREQ signal is an active high output. In the double host request mode
(that is, when HDRQ is set in the ICR), if HRP is cleared and host requests
are enabled (that is, if HREN is set and HEN is set), then the HTRQ and
HRRQ signals are active low outputs. If HRP is set and host requests are
enabled, the HTRQ and HRRQ signals are active high outputs.
9
Address
Register
Latch
Base
8
A[3–7]
7
8 bits
HEN HAEN HREN HCSEN HA9EN HA8EN HGEN
6
5
Description
4
Chip select
3
Freescale Semiconductor
2
1
0