DSP56321VF220 Freescale Semiconductor, DSP56321VF220 Datasheet - Page 3

• Manufacturer Part Number: DSP56321VF220
• Description: IC DSP 24BIT 220MHZ 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56321VF220

• Interface: Host Interface, SSI, SCI
• Clock Rate: 220MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 576kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.60V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 220MHz
• Mips: 220
• Device Input Clock Speed: 220MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 220 MHz
• Device Million Instructions Per Second: 220 MIPS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Features
Table 1 lists the features of the DSP56321 device.
Freescale Semiconductor
Coprocessor (EFCOP)
Internal Peripherals
High-Performance
Enhanced Filter
DSP56300 Core
Feature
• 275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC),
• Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
• Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)
• Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 275 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
with skew elimination
test access port (TAP)
• Real finite impulse response (FIR) with real taps
• Complex FIR with complex taps
• Complex FIR generating pure real or pure imaginary outputs alternately
• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
• Direct form 2 (DFII) IIR filter
• Four scaling factors (1, 4, 8, 16) for IIR output
• Adaptive FIR filter with true least mean square (LMS) coefficient updates
• Adaptive FIR filter with delayed LMS coefficient updates
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
six-channel home theater)
enabled
DSP56321 Technical Data, Rev. 11
Table 1. DSP56321 Features
Description
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