DSP56321VL240 Freescale Semiconductor, DSP56321VL240 Datasheet - Page 44

• Manufacturer Part Number: DSP56321VL240
• Description: IC DSP 24BIT 240MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56321VL240

• Interface: Host Interface, SSI, SCI
• Clock Rate: 240MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 576kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.60V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 240MHz
• Mips: 240
• Device Input Clock Speed: 240MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications
2-24
Notes:
No.
451 TXC rising edge to FST out (word-
452 TXC rising edge to data out enable from
453 TXC rising edge to Transmitter 0 drive
454 TXC rising edge to data out valid
455 TXC rising edge to data out high
456 TXC rising edge to Transmitter 0 drive
457 FST input (bl, wr) setup time before
458 FST input (wl) to data out enable from
459 FST input (wl) to Transmitter 0 drive
460 FST input (wl) setup time before TXC
461 FST input hold time after TXC falling
462 Flag output valid after TXC rising edge
length) low
high impedance
enable assertion
impedance
enable deassertion
TXC falling edge
high impedance
enable assertion
falling edge
edge
1.
2.
3.
4.
5.
6.
7.
For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-4) and the
ESSI control register. T
Manual . T
Block Diagram shown in Figure 7-3 of the DSP56321 Reference Manual .
The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but
spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last bit
clock of the first word in the frame.
Periodically sampled and not 100 percent tested
V
TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) Receive Frame Sync
i ck = Internal Clock; x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode (asynchronous implies that TXC and RXC are two different clocks)
i ck s = Internal Clock, Synchronous Mode (synchronous implies that TXC and RXC are the same clock)
In the timing diagrams below, the clocks and frame sync signals are drawn using the clock falling edge as a the first reference.
Clock and frame sync polarities are programmable in Control Register B (CRB). Refer to the DSP56321 Reference Manual for
details.
Characteristics
CCQH
3
= 3.3 V ± 0.3 V, V
2
ECCI
3
must be ≥ T
4, 6
ECCX
CCQL
C
× 4, in accordance with the explanation of CRA[PSR] and the ESSI Clock Generator Functional
must be ≥ T
Table 2-12.
= 1.6 V ± 0.1 V; T
Symbol Expression
DSP56321 Technical Data, Rev. 11
C
× 3, in accordance with the note below Table 7-1 in the DSP56321 Reference
J
ESSI Timings (Continued)
= 0°C to +85°C, C
Min Max Min Max Min Max Min Max
10.0
10.0
200 MHz
5.0
5.0
3.8
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12.5
12.5
12.5
13.5
12.5
30.0
12.5
15.0
15.0
18.0
12.5
8.3
8.3
8.3
8.3
8.3
8.0
8.3
—
—
—
—
—
—
L
= 50 pF
10.0
10.0
220 MHz
5.0
5.0
3.8
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12.5
12.5
12.5
13.5
12.5
30.0
12.5
15.0
15.0
18.0
12.5
8.3
8.3
8.3
8.3
8.3
8.0
8.3
—
—
—
—
—
—
10.0
10.0
240 MHz
5.0
5.0
3.8
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12.5
12.5
12.5
13.5
12.5
30.0
12.5
15.0
15.0
18.0
12.5
8.3
8.3
8.3
8.3
8.3
8.0
8.3
—
—
—
—
—
—
Freescale Semiconductor
10.0
10.0
275 MHz
5.0
5.0
3.8
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12.5
12.5
12.5
13.5
12.5
30.0
12.5
15.0
15.0
18.0
12.5
8.3
8.3
8.3
8.3
8.3
8.0
8.3
—
—
—
—
—
—
Cond-
ition
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns