MSC7119VF1200 Freescale Semiconductor, MSC7119VF1200 Datasheet - Page 55

• Manufacturer Part Number: MSC7119VF1200
• Description: DSP 16BIT W/DDR CTRLR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC711x StarCorer
• Type: Fixed Pointr

Specifications of MSC7119VF1200

• Interface: Host Interface, I²C, UART
• Clock Rate: 300MHz
• Non-volatile Memory: ROM (8 kB)
• On-chip Ram: 464kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: 400-MAPBGA
• Device Core Size: 16b
• Clock Freq (max): 300MHz
• Mips: 300
• Device Input Clock Speed: 300MHz
• Ram Size: 256KB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 1.14/2.38/3.14V
• Operating Supply Voltage (max): 1.26/2.63/3.47V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.5.1
V
the voltage supply design needs and goals:
3.5.2
The DDR decoupling considerations are as follows:
Freescale Semiconductor
TT
•
•
•
•
•
•
•
•
•
•
•
•
and V
Minimize the noise on both rails.
V
single IC to generate both signals.
Both references should have minimal drift over temperature and source supply.
It is important to minimize the noise from coupling onto V
— Isolate V
— Use 15–20 mm track.
— Use 20–30 mm clearance between other traces for isolating.
— Use the outer layer route when possible.
— Use distributed decoupling to localize transient currents and return path and decouple with an inductance less than
Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.
Use a wide island trace on the outer layer:
— Place the island at the end of the bus.
— Decouple both ends of the bus.
— Use distributed decoupling across the island.
— Place SSTL termination resistors inside the V
Place the V
— Reduce inductance and return path.
— Tie current sense pin at the midpoint of the island.
DDR memory requires significantly more burst current than previous SDRAMs.
In the worst case, up to 64 drivers may be switching states.
Pay special attention and decouple discrete ICs per manufacturer guidelines.
Leverage V
termination rail.
See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel
(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).
TT
REF
3 nH.
Driver
must track variation in the V
V
Decoupling
are isolated power supplies at the same voltage, with V
REF
TT
TT
REF
and V
regulator as closely as possible to the termination island.
island topology to minimize the number of capacitors required to supply the burst current needs of the
and shield it with a ground trace.
V
TT
DDQ
Design Constraints
REF
V
SS
Figure 37. SSTL Power Value
DC offsets. Although they are isolated supplies, one possible solution is to use a
MSC7119 Data Sheet, Rev. 8
RS
TT
island and ensure a good, solid connection.
RT
REF
TT
as follows:
as a high current power source. This section outlines
V
TT
Hardware Design Considerations
V
REF
Receiver
55