AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 496

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

34.6.12
Register Name:
Access Type:
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
34.6.13
Register Name:
Access Type:
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify-
ing the waveform period or duty-cycle.
Only the first 16 bits (internal channel counter size) are significant.
496
• the channel is enabled (writing CHIDx in the PWM_ENA register).
• the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
CPD (PWM_CMRx Register)
31
23
15
31
23
15
7
7
AT91SAM7S Series Preliminary
PWM Channel Counter Register
PWM Channel Update Register
0
1
30
22
14
30
22
14
6
6
PWM_CCNT[0..X-1]
Read-only
PWM_CUPD[0..X-1]
Write-only
The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the
beginning of the next period.
The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning
of the next period.
29
21
13
29
21
13
5
5
28
20
12
28
20
12
4
4
CUPD
CUPD
CUPD
CUPD
CNT
CNT
CNT
CNT
27
19
11
27
19
11
3
3
26
18
10
26
18
10
2
2
25
17
25
17
9
1
9
1
6175K–ATARM–30-Aug-10
24
16
24
16
8
0
8
0