MC9S08AC32CPUE Freescale Semiconductor, MC9S08AC32CPUE Datasheet - Page 99

• Manufacturer Part Number: MC9S08AC32CPUE
• Description: IC MCU 8BIT 32K FLASH 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC32CPUE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.6.10
In addition to the I/O control, port E pins are controlled by the registers listed below.
Freescale Semiconductor
PTEPE[7:0]
PTESE[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTEPE7
PTESE7
Port E Pin Control Registers (PTEPE, PTESE, PTEDS)
Internal Pullup Enable for Port E Bits— Each of these control bits determines if the internal pullup device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port E bit n.
1 Internal pullup device enabled for port E bit n.
Output Slew Rate Control Enable for Port E Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
0
0
7
7
Figure 6-25. Output Slew Rate Control Enable for Port E (PTESE)
PTEPE6
PTESE6
0
0
6
6
Figure 6-24. Internal Pullup Enable for Port E (PTEPE)
Table 6-24. PTESE Register Field Descriptions
Table 6-23. PTEPE Register Field Descriptions
PTEPE5
PTESE5
MC9S08AC60 Series Data Sheet, Rev. 2
0
0
5
5
PTEPE4
PTESE4
0
0
4
4
Description
Description
PTEPE3
PTESE3
3
0
3
0
PTEPE2
PTESE2
0
0
2
2
Chapter 6 Parallel Input/Output
PTEPE1
PTESE1
0
0
1
1
PTEPE0
PTESE0
0
0
0
0
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