MC908JL3EMPE Freescale Semiconductor, MC908JL3EMPE Datasheet - Page 50

• Manufacturer Part Number: MC908JL3EMPE
• Description: IC MCU 4K FLASH W/OSC 28-PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL3EMPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
50
Note: Writing a 0 clears SBSW.
Addr.
$FE00
$FE01
$FE02
$FE03
PIN LOGIC
Register Name
RESET
Break Status Register
Reset Status Register
INTERNAL
PULL-UP
Break Flag Control
Register (BFCR)
V
Reserved
DD
(BSR)
(RSR)
SIM RESET STATUS REGISTER
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
POR:
Figure 5-2. SIM I/O Register Summary
RESET PIN CONTROL
POR CONTROL
MC68HC908JL3E Family Data Sheet, Rev. 4
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
INTERRUPT CONTROL
CLOCK
Bit 7
BCFE
Figure 5-1. SIM Block Diagram
POR
R
R
0
1
0
= Unimplemented
PIN
6
R
R
R
0
0
CLOCK GENERATORS
RESET
COUNTER
SIM
÷2
COP
R
R
R
5
0
0
CONTROL
MASTER
RESET
ILOP
4
R
R
R
0
0
ILAD
USB RESET (FROM USB MODULE)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
2OSCOUT (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
3
R
R
R
R
0
0
= Reserved
MODRST
2
R
R
R
0
0
Freescale Semiconductor
SBSW
NOTE
LVI
1
R
R
0
0
Bit 0
R
R
R
0
0
0