MC908JL3EMPE Freescale Semiconductor, MC908JL3EMPE Datasheet - Page 62
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MC908JL3EMPE
Manufacturer Part Number
MC908JL3EMPE
Description
IC MCU 4K FLASH W/OSC 28-PDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MC908JL3EMPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
HC08JL
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (3Mb)
System Integration Module (SIM)
5.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in stop mode, stopping the CPU and
peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32.
This is ideal for applications using canned oscillators that do not require long start-up times from stop
mode.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register
(BSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
62
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
2OSCOUT
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
RST
IAB
IDB
R/W
IDB
IAB
instruction.
$A6
Figure 5-17. Wait Recovery from Internal Reset
STOP ADDR
$6E0B
$A6
Figure 5-18. Stop Mode Entry Timing
MC68HC908JL3E Family Data Sheet, Rev. 4
PREVIOUS DATA
$A6
STOP ADDR + 1
Cycles
32
NOTE
NOTE
NEXT OPCODE
Figure 5-18
Cycles
32
SAME
shows stop mode entry timing.
RST VCT H
SAME
RST VCT L
SAME
SAME
Freescale Semiconductor
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