MC9S12GC16MFAE Freescale Semiconductor, MC9S12GC16MFAE Datasheet - Page 122
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MC9S12GC16MFAE
Manufacturer Part Number
MC9S12GC16MFAE
Description
IC MCU 16K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC16MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
60
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC16MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 3 Module Mapping Control (MMCV4) Block Description
3.4
The MMC sub-block performs four basic functions of the core operation: bus control, address decoding
and select signal generation, memory expansion, and security decoding for the system. Each aspect is
described in the following subsections.
3.4.1
The MMC controls the address bus and data buses that interface the core with the rest of the system. This
includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control
of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages
all CPU read data bus swapping operations.
3.4.2
As data flows on the core address bus, the MMC decodes the address information, determines whether the
internal core register or firmware space, the peripheral space or a memory register or array space is being
addressed and generates the correct select signal. This decoding operation also interprets the mode of
operation of the system and the state of the mapping control registers in order to generate the proper select.
The MMC also generates two external chip select signals, emulation chip select (ECS) and external chip
select (XCS).
3.4.2.1
Although internal resources such as control registers and on-chip memory have default addresses, each can
be relocated by changing the default values in control registers. Normally, I/O addresses, control registers,
122
Functional Description
Bus Control
Address Decoding
Select Priority and Mode Considerations
PIX5
0
0
0
0
1
1
1
1
.
.
.
.
.
PIX4
0
0
0
0
1
1
1
1
.
.
.
.
.
Table 3-14. Program Page Index Register Bits
PIX3
MC9S12C-Family / MC9S12GC-Family
0
0
0
0
1
1
1
1
.
.
.
.
PIX2
0
0
0
0
1
1
1
1
.
.
.
.
.
Rev 01.24
PIX1
0
0
1
1
0
0
1
1
.
.
.
.
.
PIX0
0
1
0
1
0
1
0
1
.
.
.
.
.
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