MC9S12GC16MFAE Freescale Semiconductor, MC9S12GC16MFAE Datasheet - Page 415
![IC MCU 16K FLASH 25MHZ 48-LQFP](/photos/13/93/139351/mc9s12gc16mfae_sml.jpg)
MC9S12GC16MFAE
Manufacturer Part Number
MC9S12GC16MFAE
Description
IC MCU 16K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC16MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
60
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC16MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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14.2.2
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
14.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when its configured as a master and its used as an input to receive the slave select
signal when the SPI is configured as slave.
14.2.4
This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of
slave.
14.3
This section provides a detailed description of address space and registers used by the SPI.
The memory map for the SPIV3 is given below in
sum of a base address and an address offset. The base address is defined at the SoC level and the address
offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved
bits have no effect.
14.3.1
Freescale Semiconductor
1. Certain bits are non-writable.
2. Writes to this register are ignored.
3. Reading from this register returns all zeros.
Memory Map and Register Definition
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
MISO — Master In/Slave Out Pin
SCK — Serial Clock Pin
Module Memory Map
SS — Slave Select Pin
SPI Control Register 1 (SPICR1)
SPI Control Register 2 (SPICR2)
SPI Baud Rate Register (SPIBR)
SPI Status Register (SPISR)
Reserved
SPI Data Register (SPIDR)
Reserved
Reserved
MC9S12C-Family / MC9S12GC-Family
Table 14-1. SPIV3 Memory Map
Rev 01.24
Table
Use
Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
14-1. The address listed for each register is the
Access
R/W
—
R/W
—
—
R/W
R/W
R
2,(3)
(2)
2,3
2,3
(1)
1
415
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