MC9328MX1DVM20 Freescale Semiconductor, MC9328MX1DVM20 Datasheet - Page 31

• Manufacturer Part Number: MC9328MX1DVM20
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX1r

Specifications of MC9328MX1DVM20

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 110
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: -30°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

4.4.2.1
Freescale Semiconductor
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
X1)
10
11
1
2
3
4
5
6
7
8
9
DATABUS
Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Address
OE and EB assertion time
CS5 pulse width
OE negated to address inactive
Wait asserted after OE asserted
Wait asserted to OE negated
Data hold timing after OE negated
Data ready after wait asserted
OE negated to CS negated
OE negated after EB negated
Become low after CS5 asserted
Wait pulse width
WAIT Read Cycle without DMA
WAIT
CS5
OE
EB
1
Characteristic
programmable
min 0ns
10
Figure 6. WAIT Read Cycle without DMA
MC9328MX1 Technical Data, Rev. 7
4
2
11
See note 2
7
1.5T+0.24
Minimum
2T+2.2
T-1.86
56.81
0.5
3T
1T
9
–
0
0
Functional Description and Application Information
5
3.0 ± 0.3 V
8
6
Maximum
1.5T+0.85
3T+7.17
3
1020T
1019T
1020T
1.5
–
–
T
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31