71M6532D-IGTR/F Maxim Integrated Products, 71M6532D-IGTR/F Datasheet - Page 84
71M6532D-IGTR/F
Manufacturer Part Number
71M6532D-IGTR/F
Description
IC ENERGY METER 128KB 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6531D-IMRF.pdf
(120 pages)
Specifications of 71M6532D-IGTR/F
Mounting Style
SMD/SMT
Package / Case
LQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Data Sheet 71M6531D/F-71M6532D/F
84
MUX_ALT
MUX_DIV[3:0]
MUX_SYNC_E
OPT_FDC[1:0]
OPT_RXDIS
OPT_RXINV
OPT_TXE[1:0]
OPT_TXINV
OPT_TXMOD
PLL_OK
PLS_MAXWIDTH
[7:0]
PLS_INTERVAL
[7:0]
Name
2005[2]
209D[3:0]
2020[7]
2007[1:0]
2008[5]
2008[4]
2007[7:6]
2008[0]
2008[1]
2003[6]
2080[7:0]
2081[7:0]
Location
Reset
FF
00
0
0
0
0
0
0
0
0
0
0
Wake
FF
00
0
0
0
0
0
0
0
0
0
0
© 2005-2010 TERIDIAN Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dir
R
The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of inputs.
If CHOP_E[1:0] is 00, MUX_ALT is automatically asserted once per sumcycle, when
XFER_BUSY falls.
The number of states in the input multiplexer.
When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.
Selects the modulation duty cycle for OPT_TX.
Configures OPT_RX to an analog input to the optical UART comparator or as a digital
input/output, DIO1: 0 = OPT_RX, 1 = DIO1.
Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
Inverts OPT_TX when 1. This inversion occurs before modulation.
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated
when it would otherwise have been zero. The modulation is applied after any inversion
caused by OPT_TXINV.
Indicates that system power is present and the clock generation PLL is settled.
Determines the maximum width of the pulse (low going pulse).
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*T
If PLS_INTERVAL = 0, T
is disabled and pulses are output with a 50% duty cycle.
For PULSE_W and PULSE_V only: If the FIFO is used, PLS_INTERVAL must be set to
81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the
CE issues them.
OPT_FDC[1:0]
OPT_TXE[1:0]
00
01
10
11
00
01
10
11
Function
OPT_TX
DIO2
WPULSE
RPULSE
Function
50% Low
25% Low
12.5% Low
6.25% Low
I
is the sample time (397 µs). If set to 255, pulse width control
Description
I
. Where T
FDS 6531/6532 005
I
is PLS_INTERVAL.
v1.3
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