M5373EVB Freescale Semiconductor, M5373EVB Datasheet - Page 20

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M5373EVB

Manufacturer Part Number
M5373EVB
Description
KIT EVAL FOR MCF537X
Manufacturer
Freescale Semiconductor
Series
ColdFire®r
Type
MPUr
Datasheet

Specifications of M5373EVB

Contents
Module and Misc Hardware
For Use With/related Products
MCF537x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Electrical Characteristics
20
1
2
Num
FB4
FB5
FB6
FB7
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see
Timing
The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.
Data Input Setup
Data Input Hold
Transfer Acknowledge (TA) Input Setup
Transfer Acknowledge (TA) Input Hold
Characteristics” for SD_CS[3:0] timing.
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
FB_CSn, FB_OE,
Table 9. FlexBus AC Timing Specifications (continued)
FB_BE/BWEn
MCF537x ColdFire
FB_D[31:X]
FB_A[23:0]
FB_CLK
FB_R/W
FB_TS
FB_TA
Characteristic
Figure 7. FlexBus Read Timing
FB1
ADDR[31:X]
®
S0
FB2
Microprocessor Data Sheet, Rev. 4
NOTE
FB6
ADDR[23:0]
S1
DATA
FB4
S2
Symbol
t
t
FB7
t
t
CVFBCH
DVFBCH
FB5
DIFBCH
CIFBCH
Section 5.7.2, “DDR SDRAM AC
S3
FB3
Min
3.5
0
4
0
Freescale Semiconductor
Max
Unit
ns
ns
ns
ns

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