AD9861-50EB Analog Devices Inc, AD9861-50EB Datasheet - Page 34

• Manufacturer Part Number: AD9861-50EB
• Description: BOARD EVAL FOR AD9861-50
• Manufacturer: Analog Devices Inc

Specifications of AD9861-50EB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9861-50

AD9861
Table 15. Mode Pin Names and Descriptions
Pin Name
ADC_LO_PWR
FD/HD (SDO)
10/ 20
SPI_Bus_Enable (SPI_CS)
Interp0 and Interp1
RxPwrDwn
TxPwrDwn
Tx/Rx
Description
ADC Low Power Mode Option. ADC_LO_PWR is latched during the rising edge of RESET.
Logic low results in ADC operation at nominal power mode.
Logic high results in ADC consuming 40% less power than the nominal power mode.
For Flex I/O Configuration, this control applies only if the SPI bus is disabled. FD/HD (SDO) is latched during the
rising edge of RESET.
Logic low identifies that the DUT flex I/O port will be configured for half-duplex operation.
10/20 (IFACE2) is also latched during the rising edge of RESET to identify interleaved data mode or parallel data
modes.
Logic low indicates that the flex I/O will configure itself for parallel data mode.
Logic high indicates that the flex I/O will configure itself for interleaved data mode.
For flex I/O Configuration, The 10/ 20 pin control applies only if the SPI bus is disabled and the device is
configured for HD mode. 10/ 20 is latched during the rising edge of RESET.
10/ 20 (IFACE2) is used to identify interleaved data mode or parallel data modes.
Logic low indicates that the flex I/O will configure itself for HD20 mode.
Logic high indicates that the flex I/O will configure itself for HD10 mode.
SPI_CS is latched during the rising edge of RESET.
Logic low results in the SPI being disabled and SPI_DIO, SPI_CLK and SPI_SDO act as mode pins.
Logic high results in the SPI being fully operational, and some of the mode pins are disabled.
Interpolation/PLL Factor Configuration. This control applies only if the SPI bus is disabled.
SPI_DIO (Interp1) and SPI_CLK (Interp0) configure the Tx path for 1× [00], 2× [01], or 4× [10] interpolation and
also enable the PLL of the same multiplication factor.
Power-Down Control. RxPwrDwn logic level controls the power-down function of the Rx path.
Logic low results in the Rx path operating at normal power levels.
Logic high disables the ADC clock and disables some bias circuitry to reduce power consumption.
Power-Down Control. TxPwrDwn logic level controls the power-down function of the Tx path.
Logic low results in the Tx path operating at normal power levels.
Logic high disables the DAC clocks and disables some bias circuitry to reduce power consumption.
Power-Down Control. Tx/Rx pin enables the appropriate Tx or Rx path in the half-duplex mode.
A logic low disables the Tx digital clock and the I/O bus is configured as an output or three-stated.
A logic high disables the Rx digital clocks and the I/O bus is configured as high impedance inputs.
Rev. 0 | Page 34 of 52