AD9861-50EB Analog Devices Inc, AD9861-50EB Datasheet - Page 47

• Manufacturer Part Number: AD9861-50EB
• Description: BOARD EVAL FOR AD9861-50
• Manufacturer: Analog Devices Inc

Specifications of AD9861-50EB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9861-50

Table 23. Serial Registers Related to the Clock Distribution Block
Register Name
Enable IFACE2
Inv clkout (IFACE3)
Tx Inverse Sample
Interpolation Control
PLL Bypass
ADC Clock Div
Alt Timing Mode
PLL Div5
PLL Multiplier
PLL to IFACE2
Transmit (Tx) timing requires specific setup and hold times to
properly latch data through the data interface bus. These timing
parameters are specified relative to an internally generated
output reference clock. The AD9861 has two interface clocks
provided through the IFACE3 and IFACE2 pins. The transmit
timing specifications, setup and hold time, provide a minimum
required window of valid data.
Setup time (t
to a valid logic level prior to the relative output timing edge.
Hold time (t
valid data must remain on the data bus to be properly latched.
Figure 85 shows t
Note that in some cases negative time is specified, for example
with t
before the relative output clock edge.
Table 24 shows typical setup-and-hold times for the AD9861 in
the various mode configurations.
HOLD
IFACE3 (CLKOUT)
timing, which means that the hold time edge occurs
HOLD
SETUP
Tx DATA
) is the time after the output timing edge that
) is the time required for data to initially settle
SETUP
Figure 85. Tx Data Timing Diagram
and t
Register Address,
Bit(s)
Register 0x01, Bit 1
Register 0x15, Bit 3
Register 0x16, Bit 5
Register 0x01, Bit 2
Register 0x13, Bit 5
Register 0x13, Bit 1:0
Register 0x15, Bit 7
Register 0x15, Bit 5
Register 0x15, Bit 4
Register 0x15, Bit 2:0
HOLD
relative to IFACE3 falling edge.
t
SETUP
t
HOLD
Function
0: There is no clock output from IFACE2 pin, except in FD mode.
1: The IFACE2 pin outputs a continuous reference clock from the PLL output. In FD mode,
this inverts the IFACE2 output.
1: The IFACE3 clock output is inverted.
0: The Tx path data is latched relative to the output Tx clock rising edge.
1: The Tx path data is latched relative to the output Tx clock falling edge.
Sets interpolation of 1×, 2×, or 4× for the Tx path.
0: The PLL block is used to generate system clock.
1: The PLL block is bypassed to generate system clock.
1: ADC clock is one-half the Rx path frequency.
1: PLL block output is used to drive the Rx path clock.
0: PLL block output clock is not divided down.
1: PLL block output clock is divided by 5.
0: If enable IFACE2 register is set, IFACE2 outputs buffered CLKIN.
1: If enable IFACE2 register is set, IFACE2 outputs buffered PLL output clock.
0: The IFACE3 clock output is not inverted.
0: ADC clock rate equals the Rx path frequency.
0: CLKIN is used to drive the Rx path clock.
Sets multiplication factor of the PLL block to 1× (000), 2× (001), 4× (010), 8× (011), or 16x (100).
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Table 24. AD9861 Typical Tx Data Latch Timing Relative to
IFACE3 Falling Edge
Mode No.
1
2
4
5
7
8
10
Receive (Rx) path data is output after a reference output clock
edge. The time delay of the Rx data relative to a reference output
clock is called the output delay, t
possible interface clocks provided through the IFACE3 and
IFACE2 pins. Figure 86 shows t
edge. Note that in some cases negative time is specified, which
means that the output data transition occurs prior to the relative
output clock edge.
IFACE3 (CLKOUT)
Rx DATA
Mode Name
FD
Optional FD
HD20
Optional HD20
HD10
Optional HD10
Clone
Figure 86. Rx Data Timing Diagram
t
OD
OD
OD
relative to IFACE3 rising
. The AD9861 has two
t
5
5
5
5
5
5
5
setup
(ns)
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t
–2.5
–2.5
–1.5
–1.5
–2.5
–2.5
–1.5
AD9861
hold
(ns)