DR-TRC101-315-DK RFM, DR-TRC101-315-DK Datasheet - Page 11

• Manufacturer Part Number: DR-TRC101-315-DK
• Description: RFIC TRANCEIVER DEVELOPMENT KIT
• Manufacturer: RFM
• Type: Transceiver, SRRr

Specifications of DR-TRC101-315-DK

• Frequency: 315MHz
• For Use With/related Products: TRC101-315
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 583-1051

OOK/ASK Signaling
The RSSI may be used to recover an OOK/ASK signal using an external comparator, capacitively
coupled to the RSSI output. Typically, Automatic Gain Control (AGC) is used to reduce the input signal
level upon saturation of the RSSI in the presence of strong or near-field ASK signals. The TRC101 does
not have an AGC option, however, the input LNA gain is programmable. The output RSSI signal level
may be sampled upon enabling of the receiver to test if the signal level is in saturation. If saturation is
confirmed, the input LNA gain may be reduced until the RSSI output signal level falls within the RSSI
deviation range.
Wake-Up Mode
The TRC101 has an internal wake-up timer that has very low current consumption (1.5uA typical) and
may be programmed from 1ms to several days. A calibration is performed to the crystal at startup and
every 30 sec thereafter, even if in sleep mode. If the oscillator circuit is disabled the calibration circuit will
turn it on briefly to perform a calibration to maintain accurate timing and return to sleep.
The TRC101 also incorporates other power saving modes aside from the wake-up timer. Return to active
mode may be initiated from several external events:
If any of these wake-up events occur, including the wake-up timer, the TRC101 generates an external
interrupt on the nIRQ pin (5) which may be used as a wake-up signal to a host processor. The source of
the interrupt may be read out from the Status Register over the SPI bus.
Duty Cycle Mode
The duty cycle register may be used in conjunction with the wake-up timer to reduce the average current
consumption of the receiver. The duty cycle register may be set up so that when the wake-up timer
brings the chip out of sleep mode the receiver is turned on for a short time to sample if a signal is present
and then goes back into sleep and the process starts over. See the Duty Cycle Set Register. The
receiver must be disabled (RXEN bit 7 cleared in Power Management Register) and the wake-up timer
must be enabled (WKUPEN bit 1 set in Power Management Register) for operation in this mode. Figure
6 shows the timing for Duty Cycle Mode.
Low Battery Detector
The integrated low battery detector monitors the voltage supply against a preprogrammed value and
generates an interrupt when the supply voltage falls below the programmed value. The detector circuit
has 50mV of hysteresis built in.
SPI Interface
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©by RF Monolithics, Inc.
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Logic ‘0’ applied to nINT pin (16)
Low Supply Voltage Detect
FIFO Fill
SPI request
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Figure 6. Duty Cycle Mode Timing
TRC101 - 4/8/08
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