DR-TRC101-315-DK RFM, DR-TRC101-315-DK Datasheet - Page 30

• Manufacturer Part Number: DR-TRC101-315-DK
• Description: RFIC TRANCEIVER DEVELOPMENT KIT
• Manufacturer: RFM
• Type: Transceiver, SRRr

Specifications of DR-TRC101-315-DK

• Frequency: 315MHz
• For Use With/related Products: TRC101-315
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 583-1051

Duty Cycle Set Register
The duty cycle register may be used in conjunction with the wake-up timer to reduce the average current
consumption of the receiver. The duty cycle register may be set up so that when the wake-up timer
brings the chip out of sleep mode the receiver is turned on for a short time to sample if a signal is present
and then goes back into sleep and the process starts over.
The duty cycle uses the Multiplier value of the wake-up timer in part for its calculation. To calculate the
duty cycle use:
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the Duty Cycle Set Register.
Bit [7..1] – Duty Cycle Multiplier: These bits are the decimal value used to calculate the Duty Cycle or
“On time” of the Receiver after the wake-up timer has brought the TRC101 out of sleep mode.
Bit [0] – Duty Cycle Mode Enable: This bit enables the duty cycle mode when set.
NOTE: The receiver must be disabled (RXEN = ‘0’ in Power Management Register) and the wake-up
timer must be enabled (WKUPEN = ‘1’ in Power Management Register) for operation in this mode.
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Bit
15
1
Bit
14
1
where M is M[7..0] of the Wake-up Timer Period Register.
Bit
13
0
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Bit
12
0
Duty Cycle(%) = ((D[6..0] * 2 )+ 1)/M * 100
Bit
11
1
[POR=C80Eh]
Bit
10
0
Bit
9
0
Bit
8
0
DC6
Bit
7
DC5
Bit
6
DC4
Bit
5
DC3
Bit
4
DC2
Bit
3
DC1
Bit
2
DC0
Bit
TRC101 - 4/8/08
1
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DCEN
Bit
0