DR-TRC102-915-DK RFM, DR-TRC102-915-DK Datasheet - Page 6

• Manufacturer Part Number: DR-TRC102-915-DK
• Description: RFIC TRANCEIVER DEVELOPMENT KIT
• Manufacturer: RFM
• Type: Transceiver, SRRr

Specifications of DR-TRC102-915-DK

• Frequency: 900MHz ~ 929MHz
• For Use With/related Products: TRC102-915
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 583-1055

RF Monolithics, Inc.
the preamble for data recovery and the synchronization bytes for valid data recognition. The synch byte
(word) is 0x2DD4. Synch byte recognition is enabled through the FIFO Buffer tab of the RFDA. The
preamble sets the data timing and the RXC101 receiver locks on to this signal in order to recover the
data. The clock/data recovery time of the receiver may be set in the RFDA for fast (1 byte preamble) or
slow (2 byte preamble). Regardless of the clock/data recovery setting of the receiver, the TXC102 sends
a 2 byte preamble.
Configure both boards as follows:
Range Test
A range test can be performed by configuring both DR boards for a comm link as above and clicking on
the “Enable Range Test” button at the top of the Data Terminal Window. When the range test is activated
it will send a default message of “<TX> Range Test Data” and the enable button will flash red. At this
point the serial cable may be disconnected for free movement around the area of interest.
Rev00
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Enable Receiver
Enable TX Register
Enable RX FIFO
Crystal Load = 12pF
LNA Gain = max
Baseband BW = 67kHz
Valid Data Detect = Slow
FSK Deviation = 45kHz
Polarity of Mod = fo + df
AFC:
Data Rate:
Data Filter: (use defaults)
FIFO Buffer:
Enable AFC
Enable Fine Mode
Output Enable
Mode = Auto, drop Foffset
AFC = +15/-16*Fres
Enable Prescalar
R = 17 (2.4kbps)
Enable Synch Latch
Disable Sensitive Reset
FIFO Fill Start = Synch pattern
FIFO IT level = 8
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