AMMP-6530-TR2 Avago Technologies US Inc., AMMP-6530-TR2 Datasheet - Page 7

IC MMIC REJECT MXR 5-30GHZ 8-SMD

AMMP-6530-TR2

Manufacturer Part Number
AMMP-6530-TR2
Description
IC MMIC REJECT MXR 5-30GHZ 8-SMD
Manufacturer
Avago Technologies US Inc.
Series
AMMP-6530r
Datasheet

Specifications of AMMP-6530-TR2

Package / Case
8-QFN
Function
Mixer
Frequency
5GHz ~ 30GHz
Rf Type
ISM; DBS; VSAT; 802.16/WiMax; WLL; MMDS
Maximum Input Frequency
30000 MHz
Mounting Style
SMD/SMT
Maximum Operating Frequency
5000 MHz
Maximum Power Gain
- 8 dB
Operating Supply Voltage
- 3 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AMMP-6530-TR2
Manufacturer:
AVAGO/安华高
Quantity:
20 000
Biasing and Operation
The recommended DC bias condition for optimum
performance, and reliability is Vg = -1 volts. There is no
current consumption for the gate biasing because the
FET mixer was designed for passive operation. For down
conversion, the AMMP-6530 may be configured in a low
loss or high linearity application. In a low loss configura-
tion, the LO is applied through the drain (Pin8, power
divider side). In this configuration, the AMMP-6530 is a
“drain pumped mixer” . For higher linearity applications,
the LO is applied through the gate (Pin4, Lange coupler
side). In this configuration, the AMMP-6530 is a “gate
pumped mixer” (or Resistive mixer). The mixer is also
suitable for up-conversion applications under the gate
pumped mixer operation shown on page 3.
Please note that the image rejection and isolation
performance is dependent on the selection of the
low frequency quadrature hybrid. The performance
specification of the low frequency quadrature hybrid
as well as the phase balance and VSWR of the interface
to the AMMP-6530 will affect the overall mixer perfor-
mance.
7
Figure 21. Simplified MMIC Schematic.
LO/RF
Figure 22. Demonstration Board (available upon request).
7
6
5
NC
NC
Vg
drain
8
4
gate
IF1
NC
IF2
Gnd Vg
IF1
1
2
3
IF2
RF/LO

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