T5743P6-TGS Atmel, T5743P6-TGS Datasheet - Page 15

• Manufacturer Part Number: T5743P6-TGS
• Description: IC RCVR300-450MHZ ASK/FSK 20SOIC
• Manufacturer: Atmel

Specifications of T5743P6-TGS

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Other names: T5743N-TGS; T5743N-TGS; T5743P6-TG; T5743P6-TG; T5743PG-TGS; T5743PG-TGS

Figure 15. Timing Diagram for Failed Bit Check (Condition: CV_Lim ³ Lim_max)
Duration of the Bit Check
Receiving Mode
Digital Signal Processing
4569A–RKE–12/02
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
Start-up mode
T
Start-up
0
If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and T
varies for each check. Therefore, an average value for T
characteristics. T
baud-rate range causes a lower value for T
tion in polling mode.
In the presence of a valid transmitter signal, T
that signal, f
thereby results in a longer period for T
pre-burst T
If the bit check was successful for all bits specified by N
receiving mode. According to Figure 11, the internal data signal is switched to Pin DATA
in that case and the data clock is available after the start bit has been detected (Figure
22). A connected microcontroller can be woken up by the negative edge at Pin DATA or
by the data clock at Pin DATA_CLK. The receiver stays in that condition until it is
switched back to polling mode explicitly.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on
the selected baud-rate range (BR_Range). Figure 16 illustrates how Dem_out is syn-
chronized by the extended clock cycle T
counter. Data can change its state only after T
period t
The minimum time period between two edges of the data signal is limited to t
T
same time it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller.
The maximum time period for DATA to stay Low is limited to T
employed to ensure a finite response time in programming or switching off the receiver
via Pin DATA. T
the transmitter data stream. Figure 18 gives an example where Dem_out remains Low
after the receiver has switched to receiving mode.
1
DATA_min
2 3 4 5 6
ee
. This implies an efficient suppression of spikes at the DATA output. At the
of the Data signal as a result is always an integral multiple of T
Preburst
7
Sig
1
2
, and the count of the checked bits, N
DATA_L_max
3
.
Bit-check
4 5
Bit-check mode
T
6 7 8 9
Bit-check
depends on the selected baud-rate range and on T
is thereby longer than the maximum time period indicated by
10
1/2 Bit
11 12
13 14 15 16 17 18 19
Bit-check
XClk
Bit-check
. This clock is also used for the bit-check
requiring a higher value for the transmitter
Bit check failed ( CV_Lim >= Lim_max )
20
Bit-check
XClk
21 22 23 24
resulting in a lower current consump-
has elapsed. The edge-to-edge time
Bit-check
is dependent on the frequency of
Bit-check
Bit-check
. A higher value for N
DATA_L_max
, the receiver switches to
Sleep mode
is given in the electrical
T
0
Sleep
. This function is
XClk
Clk
T5743
.
. A higher
Bit-check
Bit-check
ee
15
³