T5743P6-TGS Atmel, T5743P6-TGS Datasheet - Page 4

• Manufacturer Part Number: T5743P6-TGS
• Description: IC RCVR300-450MHZ ASK/FSK 20SOIC
• Manufacturer: Atmel

Specifications of T5743P6-TGS

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -108dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Other names: T5743N-TGS; T5743N-TGS; T5743P6-TG; T5743P6-TG; T5743PG-TGS; T5743PG-TGS

RF Front-end
4
T5743
The RF front-end of the receiver is a heterodyne configuration that converts the input
signal into a 1 MHz IF signal. According to Figure 3, the front-end consists of an LNA
(low-noise amplifier), LO (local oscillator), a mixer and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency f
oscillator) generates the drive voltage frequency f
the voltage at Pin LF. f
f
tor is connected to a passive loop filter and thereby generates the control voltage V
the VCO. By means of that configuration V
f
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys-
tal. According to Figure 4, the crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
hereby of f
of the crystal and the XTO must be considered.
Figure 4. PLL Peripherals
The passive loop filter connected to Pin LF is designed for a loop bandwidth of
BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of
the LO. Figure 4 shows the appropriate loop filter components to achieve the desired
loop bandwidth. If the filter components are changed for any reason please notify that
the maximum capacitive load at Pin LF is limited. If the capacitive load is exceeded, a bit
check may no longer be possible since f
starts to evaluate the incoming data stream. Self polling does therefore also not work in
that case.
f
ing formula: f
To determine f
nominal IF frequency is f
quencies, the filter is tuned by the crystal frequency f
fixed relation between f
MODE.
XTO
XTO
LO
is determined by the RF input frequency f
. If f
by the phase frequency detector. The current output of the phase frequency detec-
LO
is determined, f
LO
. When designing the system in terms of receiving bandwidth, the accuracy
LO
LO
= f
, the construction of the IF filter must be considered at this point. The
RF
- f
LO
IF
IF
IF
XTO
is divided by factor 64. The divided frequency is compared to
= 1 MHz. To achieve a good accuracy of the filter’s corner fre-
and f
LFGND
LFVCC
DVCC
can be calculated using the following formula: f
XTO
LF
LO
. This relation is dependent on the logic level at Pin
V
V
S
S
C9
LO
LF
R1
RF
is controlled in a way that f
cannot settle in time before the bit check
and the IF frequency f
C10
C
LO
L
for the mixer. f
XTO
C9 = 4.7 nF
C10 = 1 nF
R1 = 820 W
XTO
. The VCO (voltage-controlled
. This means that there is a
LO
IF
is dependent on
using the follow-
LO
/64 is equal to
4569A–RKE–12/02
XTO
= f
XTO
LO
LF
/64.
and
for